LSISAS1068 LSI, LSISAS1068 Datasheet - Page 35

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

2.3
2.3.1
2.3.1.1
PCI Functional Description
PCI Addressing
PCI Configuration Space
post FIFO. When indicating the successful completion of a SCSI I/O, the
IOP writes the reply message frame descriptor using the Context Reply
format, which is a message context. If a SCSI I/O does not complete
successfully, the IOP uses the Address Reply format. In this case, the
IOP pops a reply message frame from the reply free FIFO, generates a
reply message describing the error, writes the reply message to system
memory, and writes the address of the reply message frame to the reply
post FIFO. The host can then read the reply message and take the
appropriate action.
The doorbell mechanism provides both a communication path that
interrupts the host system device driver and an alternative
communication path to the message queues. Since data transport
through the system doorbell occurs a single Dword at a time, use the
LSISAS1068 message queues for normal operation and data transport.
The host PCI interface complies with the PCI Local Bus Specification,
Version 3.0 and the PCI-X Addendum to the PCI Local Bus Specification,
Revision 2.0. The LSISAS1068 supports a 133 MHz, 64-bit PCI-X bus.
The LSISAS1068 provides support for 64-bit addressing with Dual
Address Cycle (DAC). The LSISAS1068 does not support 5 V PCI
signaling.
The three physical address spaces the PCI specification defines are:
The following sections describe the PCI address spaces.
The PCI Configuration Space is a contiguous 256 x 8-bit set of
addresses. The system BIOS initializes the configuration registers using
PCI configuration cycles. The LSISAS1068 decodes C_BE[3:0]/ to
PCI Functional Description
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
PCI Configuration Space
PCI I/O Space for operating registers
PCI Memory Space for operating registers
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