LSISAS1068 LSI, LSISAS1068 Datasheet - Page 47

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

2.5.2
Flash ROM Controller
The LSISAS1068 does not require a PBSRAM for any board design or
application.
The LSISAS1068 flash ROM interface provides access to nonvolatile
code and parameter storage for both the embedded ARM core and the
host system. An 8-bit wide flash ROM is optional if the LSISAS1068 is
not the boot device, and a suitable driver exists to initialize the
LSISAS1068 and download its code. The flash ROM interface:
Byte lane 3 of the LSISAS1068 external memory bus (MAD[31:24])
connects to the 8-bit data bus on the flash ROM. BWE[3]/ provides the
write enable signal for the flash ROM. MOE[1]/ enables the flash ROM
to drive data.
The LSISAS1068 determines the flash ROM addressable space during
the Power-On Sense configuration. If the flash ROM addressable space
is 64 Kbytes or less, then the LSISAS1068 defines only the middle
(MAD[15:8]) and lower (MAD[7:0]) address ranges during a read or write.
If the flash ROM addressable space is 128 Kbytes or greater, then the
LSISAS1068 defines the upper (MAD[23:16]), middle (MAD[15:8]), and
lower (MAD[7:0]) address ranges.
The firmware requirements for the flash ROM are:
External Memory Interface
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
–
Integrated RAID implementation
–
–
uses an 8-bit data bus
reads 4 bytes from the flash ROM and returns the resulting 32-bit
Dword for each Dword read request
writes a single data byte/word for each flash ROM write request
1 Mbyte (1 Mbit x 8) or larger flash ROM size
The LSISAS1068 has no memory requirements in this
configuration, assuming that the intelligent IOP can download the
firmware image to the LSISAS1068 and store the persistent data.
The LSISAS1068 requires a flash ROM for Integrated RAID
implementations.
The LSISAS1068 requires an NVSRAM for all
Integrated Mirroring implementations.
2-21