LSISAS1068 LSI, LSISAS1068 Datasheet - Page 61

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

Table 3.10
3.7
Table 3.11
Signal Name BGA Position
MOE[1:0]/
MWE[1:0]/
BWE[3:0]/
NVSRAM_CS/ K24
PBSRAM_CS/ M23
FLASH_CS/
Signal Name
ISTWI_CLK
ISTWI_DATA
UART_RX
UART_TX
Communication Signals
Memory Interface Signals (Cont.)
UART and I
H26, M26
K26, N26
P26, L26, P25, P22 O
L23
BGA Position Type
H23
D24
E23
H22
Table 3.11
Communication Signals
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
2
C Signals
describes the I
Type Description
O
O
O
O
O
I/O
I/O
I
O
Asserting the active LOW Memory Output Enable signals
enable the selected PBSRAM, flash ROM, or NVSRAM
device to drive data. MOE[1]/ enables flash ROM devices.
MOE[0]/ enables NVSRAM devices. MOE[1:0]/ allow
interleaved PBSRAM configurations.
The LSISAS1068 uses the active LOW Memory Bank
Write Enable signals for interleaved PBSRAM
configurations.
Asserting the active LOW Byte-lane Write Enable signals
enable partial word writes to the PBSRAM. BWE[3]/ and
BWE[2]/ enable partial word writes to the flash ROM and/or
the NVSRAM if FLASH_CS/ or NVSRAM_CS/ are
asserted.
Asserting the active LOW NVSRAM Chip Select signal
selects the NVSRAM.
Asserting the active LOW RAM Chip Select signal selects
the PBSRAMs. The LSISAS1068 supports up to four
PBSRAMs in an interleaved and depth-expanded
configuration.
Asserting the active LOW Flash Chip Select signal selects
the flash ROM. The LSISAS1068 maps the flash ROM
address space into system memory.
Description
The I
The I
This signal is the UART Receive signal.
This signal is the UART Transmit signal.
2
C and UART signals.
2
2
C Clock pin provides the I
C Data pin provides the I
2
C data signal.
2
C clock signal.
3-9