LSISAS1068 LSI, LSISAS1068 Datasheet - Page 74

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

4-4
PCI Host Register Description
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Interrupt Disable
Clearing this bit enables the PCI function to assert its
interrupt signal (INTA/). Setting this bit disables the PCI
function from asserting its interrupt signal.
Fast Back-to-Back Enable
This bit determines if the master can perform fast back-
to-back transactions to different devices. Clearing this bit
indicates that fast back-to-back transactions are permit-
ted to only the same device. Setting this bit indicates that
the master can perform fast back-to-back transactions to
different devices. To set this bit, all devices on the PCI
bus must support fast back-to-back transactions.
SERR/ Enable
Setting this bit enables the LSISAS1068 to activate the
SERR/ driver. Clearing this bit disables the SERR/ driver.
Reserved
This bit is reserved.
Enable Parity Error Response
Setting this bit enables the LSISAS1068 PCI function to
detect parity errors on the PCI bus and report these
errors to the system. Clearing this bit causes the
LSISAS1068 PCI function to set the Detected Parity Error
bit, bit 15 in the PCI
when the PCI function detects a parity error. This bit only
affects parity checking. The PCI function always
generates parity for the PCI bus.
Reserved
This bit is reserved.
Write and Invalidate Enable
Setting this bit enables the PCI function to generate write
and invalidate commands on the PCI bus when operating
in the conventional PCI mode.
Reserved
This bit is reserved.
Enable Bus Mastering
Setting this bit allows the PCI function to behave as a PCI
bus master. Clearing this bit disables the PCI function
from generating PCI bus master accesses.
Status
register, but not assert PERR/
10
9
8
7
6
5
4
3
2