LSISAS1068 LSI, LSISAS1068 Datasheet - Page 23

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LSISAS1068

Manufacturer Part Number
LSISAS1068
Description
Manufacturer
LSI
Datasheet

Specifications of LSISAS1068

Lead Free Status / RoHS Status
Not Compliant

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1.6.3
PCI Performance
This section describes the PCI features:
Summary of LSISAS1068 Features
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
133 MHz, 64-bit PCI/PCI-X interface that:
Provides unequaled performance through the Fusion-MPT
architecture
Provides high throughput and low CPU utilization to off load the host
processor
Uses a dedicated ARM966 processor
Presents a single electrical load to the PCI Bus
Reduces Interrupt Service Routine (ISR) overhead with interrupt
coalescing
Supports Message Signaled Interrupts (MSI) and MSI-X
Supports 32-bit or 64-bit data bursts with variable burst lengths
Supports the PCI Cache Line Size register
Supports the PCI Memory Write and Invalidate, Memory Read Line,
and Memory Read Multiple commands
Supports the PCI-X Memory Read Dword, Split Completion, Memory
Read Block, Memory Write Block commands
Operates up to 133 MHz PCI-X
Operates at 33 MHz or 66 MHz PCI
Supports 32-bit or 64-bit data transfers
Supports 32-bit or 64-bit addressing through Dual Address
Cycles (DAC)
Provides a theoretical 1066 Mbyte/s PCI bandwidth
Supports 3.3 V PCI, and is not 5 V PCI tolerant
Complies with the PCI Local Bus Specification, Revision 3.0
Complies with the PCI-X Addendum to the PCI Local Bus
Specification, Revision 2.0
Complies with the PCI Power Management Interface
Specification, Revision 1.2
Complies with the PC2001 Specification
1-9

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