PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 242

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
15.5.2
The DCT coefficients associated with the macroblock are
output to a separate memory area and each DCT coeffi-
cient is represented as one 32-bit quantity (16 bits of run
and 16 bits of level). For intra blocks, the DC term is ex-
pressed as 16 bits of DC size and a 16-bit value whose
most significant bits (the number of bits used for DC level
is determined by DC size) represent the DC level. Each
block of DCT coefficients is terminated by a run value of
‘0xff’.
15.6
The PNX1300 VLD is targeted for a single bitstream de-
code and there is no provision to decode more than one
bitstream at a time by using the VLD in time multiplexed
mode. However internal development has shown that up
to 4 simultaneous MPEG1 bitstreams can be decoded.
This procedure is beyond the scope of this databook but
can be discussed further by contacting customer sup-
port.
15.7
To ensure compatibility with future devices, any unde-
fined MMIO bits should be ignored when read, and writ-
ten as ‘0’s.
15-4
Figure 15-3. MPEG1 Macroblock Header Output Format
First Forward Motion Vector
First Backward Motion Vector
31
31
31
31
VLD TIME SHARING
MMIO REGISTERS
Run-Level Output Data
30
30
25
Esc Count
PRELIMINARY SPECIFICATION
Motion Code [0][0][0]
Motion Code [0][1][0]
29
29
17
MBA Inc
Motion Residual [0][0][0]
23
Motion Residual [0][1][0]
23
11
MB Type
6
15.7.1
This register contains the current status information most
pertinent to the normal operation of an MPEG video de-
code application. VLD status description is detailed in
Table 15-3
ter hardware reset) is ‘0’.
Interrupts can be enabled for any of the defined status
bits (see following VLD_IMASK description). Acknowl-
edgment of the interrupt is done by writing a ‘1’ to the cor-
responding bit in VLD_STATUS register. Writing a one to
the bits one through five clears the corresponding bits.
However bit 0 (COMMAND_DONE) is cleared only by is-
suing a new command. Writing a ‘0’ to bit 0 of the status
register will result in undefined behavior of the VLD. Note
that several status bits may be asserted simultaneously.
Thus it is recommended to use level triggered interrupts
(see
knowledge the interrupt.
15.7.2
This register allows the DSPCPU to control the initiation
of the interrupt for the corresponding bits in the VLD Sta-
tus Register. Writing a ‘1’ into any of the defined
VLD_IMASK bits enables the interrupt for the corre-
sponding bit in the status register (VLD_STATUS). De-
fault value (after hardware reset) is ‘0’.
15
15
4
Section 3.5.3.6 on page
Motion Code [0][0][1]
VLD Status (VLD_STATUS)
VLD Interrupt Enable (VLD_IMASK)
Motion Code [0][1][1]
13
and pictured in
13
3
14
12
2
Figure
Philips Semiconductors
7
7
Motion Residual [0][0][1]
10
Motion Residual [0][1][1]
3-11) and carefully ac-
CBP
15-4. Default value (af-
1
quant scale
4
0
w0
w1
w2
w3