PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 61

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
3.2
3.2.1
In the PNX1300 architecture, all operations can be op-
tionally 'guarded'. A guarded operation executes condi-
tionally, depending on the value in the ‘guard' register.
For example, a guarded add is written as:
This should be taken to mean
The ’if R23' clause controls the execution of the opera-
tion based on the LSB of R23. Hence, depending on the
LSB of R23, R13 is either unchanged or set to contain
the integer sum of R14 and R10.
Guarding applies to all DSPCPU operations, except iimm
and uimm (load-immediate). It controls the effect on all
programmer-visible states of the system, i.e. register val-
ues, memory content, exception raising and device state.
3.2.2
Memory is byte addressable. Loads and stores must be
‘naturally aligned’, i.e. a 16-bit load or store must target
an address that is a multiple of 2. A 32-bit load or store
must target an address that is a multiple of 4. The BSX
bit in the PCSW determines the byte order of loads and
stores. For example, see
“PNX1300/01/02/11 DSPCPU Operations.”
Only 32-bit load and store operations are allowed to ac-
cess MMIO registers in the MMIO address aperture (see
Section 3.4, “Memory and
fined for other loads and stores. A load from a non-exis-
tent MMIO register returns an undefined result. A store to
a non-existent MMIO register times out and then does
not happen. There are no other side effects of an access
to a nonexistent MMIO register. The state of the BSX bit
has no effect on the result of MMIO accesses.
Loads are allowed to be issued speculatively. Loads out-
side the range of valid data memory addresses for the
active process return an implementation-dependent val-
ue and do not generate an exception. Misaligned loads
also return an implementation dependent value and do
not generate an exception.
If a pair of memory operations involves one or more com-
mon bytes in memory, the effect on the common bytes is
as defined in
Table 3-4
minimum values of implementation-dependent address-
ing-mode components are shown in
if R23 then R13 ← R14 + R10.
Note: The index and scaled-index modes are not
allowed with store opcodes, due to the hardware
IF R23 iadd R14 R10 → R13
INSTRUCTION SET OVERVIEW
Guarding (Conditional Execution)
Load and Store Operations
shows the supported addressing modes. The
Table
3-6.
MMIO”). The results are unde-
ld32
and
st32
Table
in
3-5.
Appendix A,
Table 3-6. Behavior of loads and stores with
coincident addresses
The scale factor applied (1/2/4) in the scaled addressing
modes is equal to the size of the item loaded or stored,
i.e. 1 for a byte operation, 2 for a 16-bit operation and 4
for a 32-bit operation.
Table 3-7
for the three addressing modes.
Table 3-7. Load and store mnemonics
Example usage of load and store operations:
PRELIMINARY SPECIFICATION
8-bit signed load
8-bit unsigned load
16-bit signed load
16-bit unsigned load
32-bit load
8-bit store
16-bit store
32-bit store
T
T
T
T
store1
T
store1
Condition
store
store
restriction that each operation have at most 2 source
operand registers and 1 condition register. Stores
use 1 operand register for the value to be stored
leaving only 1 register to form an address.
load
IF r10 ild16d(12) r12 → r13
IF r10 st32d(40) r12 r13
Operation
< T
< T
= T
< T
= T
If the LSB of r10 is set, load 16 bits starting at
address (r12+12) using the byte ordering indicated
in PCSW.BSX, sign-extend the value to 32 bits and
store the result in r13.
If the LSB of r10 is set, store the 32-bit value from
r13 to the address (r12+40) using the byte ordering
indicated in PCSW.BSX.
store
store2
store2
load
load
lists the available load and store mnemonics
If a store is issued before a load, the value
loaded contains the new bytes.
If a load is issued before a store, the value
loaded contains the old bytes.
If store1 is issued before store2, the result-
ing value contains the bytes of store2.
If a load and store are issued in the same
clock cycle, the result is UNDEFINED.
If two stores are issued in the same clock
cycle, the resulting stored value is unde-
fined.
ild8d
uld8d
ild16d
uld16d
ld32d
st8d
st16d
st32d
Displacement
DSPCPU Architecture
Behavior
uld8r
ild16r
uld16r
—
ild8r
ld32r
—
—
Index
—
—
ild16x
uld16x
ld32x
—
—
—
Scaled-
Index
3-5