PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 87

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Figure 5-5. Formats of the registers in charge of data-cache locking.
‘1’. Setting DC_LOCK_ENABLE to ‘0’ causes no action
except to allow the previously locked blocks to be re-
placement victims.
To program a new lock range, the following sequence of
operations is used:
1. Disable cache locking by writing ‘0’ to
2. Define a new lock range by writing to
3. Enable cache locking by writing ‘1’ to
Dirty locked blocks can be written back to main memory
while locking is enabled by executing copyback opera-
tions in software.
Programmer’s note: Software should not execute din-
valid operations on a locked block. If it does, the block
will be removed from the cache, creating a ‘hole’ in the
lock range (and the data cache) that cannot be reused
until locking is deactivated.
Cache locking is disabled by default when PNX1300 is
reset.
The RESERVED field in DC_LOCK_CTL should be ig-
nored on reads and written as all zeroes.
Locking should not be enabled by PCI accesses to the
MMIO registers.
5.3.8
Bits 6 and 5 in DC_LOCK_CTL comprise the
APERTURE_CONTROL field. This field can be used to
change the memory map as seen by the DSPCPU. The
hardware RESET value of the field corresponds to the
memory map as described in
Map.”
Figure 5-6 Formats of the DRAM_CACHEABLE_LIMIT register.
MMIO_BASE
0x10 0008
0x10 0010
0x10 0014
0x10 0018
DC_LOCK_ENABLE.
DC_LOCK_ADDR and DC_LOCK_SIZE.
DC_LOCK_ENABLE.
MMIO_BASE
offset:
offset:
Memory Hole and PCI Aperture
Disable
DRAM_CACHEABLE_LIMIT
(r/w)
DC_LOCK_CTL (r/w)
DC_LOCK_ADDR (r/w)
DC_LOCK_SIZE (r/w)
Section 3.4.1, “Memory
31
0 0 0 0 0 0
0 0
31
0 0
DRAM_CACHEABLE_LIMIT_FIELD
27
0 0
27
DC_LOCK_ADDRESS
0 0
0 0
23
0 0 0 0 0 0
0 0
23
Table 5-6. Aperture control field
5.3.9
The data cache supports one non-cacheable address re-
gion within the DRAM address space aperture. The base
address of this region is determined by the value in the
DRAM_CACHEABLE_LIMIT MMIO register, which is
shown in
tions always incur many stall cycles, the non-cacheable
region should be used sparingly.
A memory operation is non-cacheable if its target ad-
dress satisfies:
Thus, the non-cacheable region is at the high end of the
DRAM
DRAM_CACHEABLE_LIMIT register forces the size of
the non-cacheable region to be a multiple of 64 KB.
When PNX1300 is reset, DRAM_CACHEABLE_LIMIT is
set equal to DRAM_LIMIT, which results in a zero-length
non-cacheable region.
Programmer’s note: When DRAM_CACHEABLE_LIMIT
is changed to enlarge the region that is non-cacheable,
software must ensure coherency. This is accomplished
by explicitly copying back dirty data (using dcb opera-
tions) and invalidating (using dinvalid operations) the
cache blocks in the previously unlocked region.
PRELIMINARY SPECIFICATION
0 0
00 (RESET) Normal operation memory map
01
10
11
[dram_cacheable_limit] <= address < [dram_limit]
Value
19
0 0
19
Non-cacheable Region
0 0 0 0 0 0
0 0
Figure
aperture.
• loads to 0..0xff always return 0 and cause no
• PCI aperture(s) are enabled
• loads to address 0..0xff cause a PCI read, i.e.
• PCI aperture(s) are enabled
PCI apertures are disabled for loads
• loads return a 0 and cause no PCI read
RESERVED for future extensions
15
0
PCI read (memory hole is enabled)
the memory hole is disabled
15
APERTURE_CONTROL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5-6. Since uncached memory opera-
0
0 0
0
Memory map properties
DC_LOCK_SIZE
11
0 0 0 0 0
0 0
The
11
0 0
Cache Architecture
DC_LOCK_ENABLE
0 0
format
7
7
6
0 0 0 0 0 0
0
5
(Section
0 0 0 0 0
reserved
3
3
of
3.4.1):
0
5-5
the
0