PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 243

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Table 15-3. VLD_STATUS register
15.7.3
The VLD_CTL register has one bit indicating the endian-
ness of the VLD unit. Little-Endian = ‘1’, Big-Endian = ‘0’.
Default value (after hardware reset) is ‘0’.
Table 15-4. VLD control (R/W)
15.8
There are one input DMA engine and two output DMA
engines in the VLD block. Each of the three DMA en-
gines (or channels) for the VLD is controlled by two
MMIO registers. The address register always contains
the address of the next SDRAM transaction. The count
register always indicates the amount of data to be trans-
ferred to or from main memory. A DMA completes when
its count reaches zero. Once a DMA count register be-
comes zero, a bit is set in the status register and the
COMMAND_DONE
STARTCODE
ERROR
DMA_IN_DONE
MBH_OUT_DONE
RL_OUT_DONE
Reserved
Little Endian
Name
Name
VLD DMA REGISTERS
VLD Control (VLD_CTL)
(bits)
Size
(bits)
Size
1
1
1
1
1
1
1
1
Indicates successful completion
of current command
VLD encountered 0x000001
while executing parse or next
start code command
VLD encountered an illegal
Huffman code or an unexpected
start code
DMA transfer of given SDRAM
buffer has completed and VLD
is stalled waiting on more main
memory input data; DSPCPU is
responsible to provide the new
SDRAM buffer to VLD
Macroblock Header DMA trans-
fer has completed
Run-level DMA transfer com-
plete
Forces VLD to operate in Little
Endian Mode when set to 1.
Description
Description
DSPCPU can be interrupted. The DSPCPU sets a non-
zero value to a DMA count register to initiate a new DMA
transaction. The input count register always contains
number of bytes to be fetched from the main memory.
The output count registers always contain the number of
words (4 bytes) to be written to the main memory.
Note that both of the DMA output engines write only to
64-byte aligned addresses and they always write 64
bytes. When flushing the DMA output FIFOs there may
not be 64 bytes of valid data at the time the flush com-
mand is received. In this case, 64 bytes are still written to
the main memory. The valid bytes can be determined
from the count register value before issuing the flush
command. The valid data always resides in the first N
bytes while the last 64-N bytes will contain random data
and should be ignored.
15.8.1
The bitstream input to the VLD is controlled by
VLD_BIT_ADR and VLD_BIT_CNT MMIO registers.
VLD_BIT_ADR contains the main memory address for
the next read from the main memory to the VLD input
FIFO. VLD_BIT_CNT register contains the number of
bytes remaining to be read before the current DMA is
completed.
The VLD input address is byte aligned.
15.8.2
The macroblock header output of the VLD is controlled
by VLD_MBH_ADR and VLD_MBH_CNT registers.
VLD_MBH_ADR contains the address of the next write
of macroblock header data to the main memory.
VLD_MBH_CNT contains the remaining number of
words (4 bytes) to write before the current DMA expires.
The macroblock header output address is 64-byte
aligned.
15.8.3
The run-level output of the VLD is controlled by
VLD_RL_ADR and VLD_RL_CNT. VLD_RL_ADR con-
tains the address of the next write of macroblock header
data to the main memory. VLD_RL_CNT contains the
number of 4-byte writes remaining before the current
DMA expires.
The run-level buffer address is 64-byte aligned.
PRELIMINARY SPECIFICATION
DMA Input
Macroblock Header Output DMA
Run-Level Output DMA
Variable Length Decoder
15-5