PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 262

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
17.9
The SSI unit has two test modes which can be controlled
by setting SSI_CSR.TMS. A remote and a local loop
back testmode are supported (see also
17.9.1
This test mode allows a remote transmitter to test itself,
the intervening transmission media, and its associated
receiver. In this mode, the data received on the
SSI_RxDATA pin is buffered and transmitted on the
SSI_TxDATA pin. The data is not transferred to
SSI_TxDR/TxFIFO and the DSPCPU is never interrupt-
ed. The transmitter is clocked by the SSI_RxCLK pin with
a combinatorial clock delay.
17.9.2
This test mode allows the DSPCPU to run local checks
of the SSI. Data written to the TxFIFO is serialized and
17-8
Figure 17-10. SSI MMIO registers.
MMIO_BASE
0x10 2C00
0x10 2C04
0x10 2C10
0x10 2C20
0x10 2C24
reset: 0x00f00000
reset: 0x0000f000
offset:
SSI TEST MODES
Local Loopback
Remote Loopback
SSI_CTL (r/w)
SSI_CSR (r/w)
SSI_TXDR (w/o)
SSI_RXDR (r/o)
SSI_RXACK (w/o)
PRELIMINARY SPECIFICATION
TXR
RXR
TMS
31
31
TXE
31
CDE
RXE
Table
TCP
CD2
RCP
SLP
TSD
17-9).
RSD
27
27
27
CTUE
23
23
23
IO1 IO2
SROE
passed to the receiver via an internal serial connection.
The receiver deserializes the data and passes it to the
RxFIFO register. Interrupts will be generated if enabled.
During local loop back mode, the data on the
SSI_RxDATA pin is ignored and the SSI_TxDATA pin is
tristated. An external CLK must be provided during local
loop back mode or no transmission or reception will oc-
cur.
17.10 MMIO REGISTERS
The MMIO Control and Status registers are shown in
Figure
Table
Table
any undefined MMIO bits should be ignored when read,
and written as ‘0’s.
CFES
WIO1
CCDS
WIO2
19
19
19
17-5,
17-9. To ensure compatibility with future devices,
TIE
17-10. The register fields are described in
RIE
TXDATA
RXDATA
Table
15
15
15
WAW
FSS
17-6,
11
11
11
Table
Philips Semiconductors
FMS
WAR
VSS
FSP
TDE
MOD
RDF
17-7,
EMS
TUE
7
ROE
7
7
FES
Table
CDS
RIO1
RIO2
RX_ACK
3
3
3
17-8, and
ILS
0
0
0