PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 370

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Hardware 8-bit store with displacement
SYNTAX
FUNCTION
DESCRIPTION
address formed from the sum rsrc2 + d. The value of the opcode modifier d must be in the range -64 and 63 inclusive.
This operation does not depend on the bytesex bit in the PCSW since only a single byte is stored.
modification of the addressed memory location (and the modification of cache if the location is cacheable). If the LSB
of rguard is 1, the store takes effect. If the LSB of rguard is 0,
LRU and other status bits in the data cache are not affected.
EXAMPLES
r10 = 0xd00, r80 = 0x44332211
r50 = 0, r20 = 0xd01,
r70 = 0xaabbccdd
r60 = 1, r30 = 0xd02,
r70 = 0xaabbccdd
The
The
[ IF rguard ] h_st8d(d) rsrc1 rsrc2
if rguard then
h_st8d
h_st8d
mem[rsrc2 + d] ← rsrc1<7:0>
Initial Values
operation stores the least-significant 8-bit byte of rsrc1 into the memory location pointed to by the
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
h_st8d(3) r80 r10
IF r50 h_st8d(-4) r70 r20
IF r60 h_st8d(-4) r70 r30
Operation
PRELIMINARY SPECIFICATION
h_st8d
PNX1300/01/02/11 DSPCPU Operations
has no side effects whatever; in particular, the
[0xd03] ← 0x11
no change, since guard is false
[0xcfe] ← 0xdd
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
st8 st8d st16 st16d st32
ATTRIBUTES
SEE ALSO
Result
st32d
h_st8d
–64..63
dmem
7 bits
4, 5
n/a
29
2
A-72