PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 64

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
for PC-hosted PNX1300 boards; its final location is de-
termined by the boot EEPROM for standalone systems.
See
Figure 3-5
ory map (addresses used are offsets with respect to the
MMIO base). The operating system on PNX1300 can
change MMIO_BASE by writing to the MMIO_BASE
MMIO location. User programs should not attempt this.
Refer to the TriMedia SDE Reference Manual for the
standard method to access the device registers from C
language device drivers.
Only 32-bit load and store operations are allowed to ac-
cess MMIO registers in the MMIO address aperture. The
results are undefined for other loads and stores. Reads
from non-existent MMIO registers return undefined val-
ues. Writes to nonexistent MMIO registers time out.
There are no side effects of accesses to nonexistent
MMIO registers. The state of the PCSW BSX bit has no
effect on the result of MMIO accesses.
The Icache tag and LRU bit access aperture give the
DSPCPU read-only access to the Icache status. Refer to
Section 5.4.8, “Reading Tags and Cache Status”
tails.
The EXCVEC MMIO location is explained in
3.5.2, “EXC (Exceptions).” Section 3.5.3, “INT and NMI
(Maskable and Non-Maskable Interrupts),”
the locations that deal with the setup and handling of in-
Figure 3-5. Memory map of MMIO address space (addresses are offset from MMIO_BASE).
3-8
Chapter 13, “System Boot”
0x1F FFFFF
gives a detailed overview of the MMIO mem-
0x10 2C00
0x10 1C00
0x10 0C00
0x10 3800
0x10 3400
0x10 3000
0x10 2800
0x10 2400
0x10 2000
0x10 1800
0x10 1400
0x10 1000
0x10 0800
0x10 0400
0x10 0000
0x01 0000
0x00 0000
Main memory, cache control
Vectored interrupt controller
PRELIMINARY SPECIFICATION
Icache tags & LRU (r/o)
Image coprocessor
VLD coprocessor
JTAG interface
Debug support
Future Use
PCI interface
SSI interface
Future Use
I
MMIO base
Reserved
2
Reserved
Audio Out
Video Out
C interface
Audio In
Video In
Timers
for
for
for more information.
describes
Section
for de-
terrupts: ISETTING, IPENDING, ICLEAR, IMASK and
the interrupt vectors. The timer MMIO locations are de-
scribed in
data breakpoint are described in
Support.”
ed in the respective device chapters.
3.5
The PNX1300 microprocessor responds to the special
events shown in
With the exception of RESET, which is enabled at all
times, the architecture of the DSPCPU allows special
event handling to begin only during an interruptible jump
operation (ijmpt, ijmpf or ijmpi) that succeeds (i.e., is a
taken jump). EXC, NMI and INT handling can be initiated
during handling of an EXC or an INT, but only during suc-
cessful interruptible jumps.
Table 3-9. Special Events and Event Vectors
RESET (Highest priority) vector to DRAM_BASE
Event
NMI,
EXC
INT
0x10 0C60
0x10 0C40
0x10 0C20
0x10 0C00
0x10 081C
0x10 08F8
0x10 1200
0x10 1000
0x10 08Fc
0x10 0888
0x10 0884
0x10 0880
0x10 0828
0x10 0824
0x10 0820
0x10 0818
0x10 0814
0x10 0810
0x10 0800
0x10 0400
0x10 0004
0x10 0000
SPECIAL EVENT HANDLING
(All exceptions) vector to EXCVEC (programmable)
(Non-maskable interrupt, maskable interrupt) use
the programmed vector (one of 32 vectors depend-
ing on the interrupt source)
The MMIO locations of each device are treat-
Section 3.8, “Timers.”
Table
instruction breakpoints
data breakpoints
DRAM_BASE
MMIO_BASE
DRAM_LIMIT
3-9, ordered by priority.
systimer
intvec31
intvec30
ipending
isetting3
isetting2
isetting1
isetting0
intvec2
intvec1
intvec0
excvec
timer3
timer2
timer1
imask
iclear
Philips Semiconductors
Vector
Section 3.9, “Debug
The instruction and