PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 517

PNX1302EH

Manufacturer Part Number
PNX1302EH
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PNX1302EH

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Endian-ness
C.1
In this document, the generic PNX1300 name refers
to the PNX1300 Series, or the PNX1300/01/02/11
products.
PNX1300 was designed to support both Little and Big
Endian systems. The PCI system bus (controlled by the
PCI Interface Unit (BIU)) operates in Little Endian mode
in both systems. This document describes how the dual
endian-ness feature is handled in PNX1300.
C.2
In Big Endian mode, a given word address (32-bit) base
corresponds to the most significant byte (MSB) of the
word. Increasing the byte address generally means de-
Figure C-1. Big and Little Endian address references
Figure C-2. Data conversion from Big Endian to Little Endian (BSW)
int w = 0x04050607;
char *cp = (char *)&w;
int w = 0x04050607;
char *cp = (char *)&w;
PURPOSE
LITTLE AND BIG ENDIAN
ADDRESSING CONVENTIONS
Little Endian Mode
Big Endian Mode
31
cp+0
04
Big Endian Mode
cp+1
05
cp+2
31
06
31
cp+0
04
cp+3
07
creasing the significance of the byte being accessed. In
Little Endian mode, the same word address base refers
to the least significant byte (LSB) of that word. Increasing
the byte address generally means increasing the signifi-
cance of the byte being accessed. This addressing con-
vention is shown in
In
a 32-bit constant in hex format assigned to the variable
‘w’ (assumes ‘int’ is 32-bit) and its address is copied into
the byte (character) pointer variable ‘cp’. The value of ad-
dress referenced by the ‘cp’ has a value of ‘0x04’ in Big
Endian machine and a value of ‘0x07’ in Little Endian ma-
chine.
It is possible to transfer from one endian-ness to another
just by swapping the bytes within a word as shown in
ure
PRELIMINARY SPECIFICATION
cp+3
07
Figure
cp+1
cp+2
05
C-2.
06
0
C-1, there is a two-line ‘C’ code which defines
cp+2
cp+1
31
06
05
cp+3
04
Little Endian Mode
by Selliah Rathnam, Luis Lucas
Figure
cp+3
07
cp+0
04
cp+2
05
C-1.
0
Appendix C
0
cp+1
06
cp+0
07
0
Fig-
C-1

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