PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 456

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Rotate left
SYNTAX
FUNCTION
DESCRIPTION
specify an unsigned rotate amount, and rdest is set to rsrc1 rotated left by this amount. The most-significant n bits of
rsrc1, where n is the rotate amount, appear as the least-significant n bits in rdest.
modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is unchanged.
EXAMPLES
r60 = 0x20, r30 = 3
r10 = 0, r60 = 0x20, r30 = 3
r20 = 1, r60 = 0x20, r30 = 3
r70 = 0xfffffffc, r40 = 2
r80 = 0xe, r50 = 0xfffffffe
As shown below, the
The
[ IF rguard ] rol rsrc1 rsrc2 → rdest
if rguard then {
}
rsrc1
n ← rsrc2<4:0>
rdest<31:n> ← rsrc1<31–n:0>
rdest<n–1:0> ← rsrc1<31:32–n>
31
rol
Intermediate result
Initial Values
(example: n = 9)
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
31
rol
operation takes two arguments, rsrc1 and rsrc2. The least-significant five bits of rsrc2
rol r60 r30 → r90
IF r10 rol r60 r30 → r100
IF r20 rol r60 r30 → r110
rol r70 r40 → r120
rol r80 r50 → r125
rdest
23
31
32 bits from rsrc1
Operation
0
Left rotator
PRELIMINARY SPECIFICATION
rsrc2
31
0
9
31
r90 ← 0x100
no change, since guard is false
r110 ← 0x100
r120 ← 0xfffffff3
r125 ← 0x80000003 (r50 is effectively equal to 0x1e)
PNX1300/01/02/11 DSPCPU Operations
23
0
roli asr asri lsl lsli lsr
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
32 bits from rsrc1
Five LSBs of rsrc2
Result
ATTRIBUTES
SEE ALSO
lsri
4
n
shifter
1, 2
No
97
—
0
2
1
A-158
rol
0