PNX1302EH NXP Semiconductors, PNX1302EH Datasheet - Page 385

• Manufacturer Part Number: PNX1302EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1302EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
ifixieee
SYNTAX
FUNCTION
DESCRIPTION
writes the result into rdest. Rounding is according to the IEEE rounding mode bits in PCSW. If rsrc1 is denormalized,
zero is substituted before conversion, and the IFZ flag in the PCSW is set. If
such as overflow or underflow, the corresponding exception flags in the PCSW are set. The PCSW exception flags
are sticky: the flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit
writepcsw
other floating-point compute operations update the PCSW at the same time, the net result in each exception flag is the
logical OR of all simultaneous updates ORed with the existing PCSW value for that exception flag.
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
A-87
r30 = 0x40400000 (3.0)
r35 = 0x40247ae1 (2.57)
r10 = 0,
r40 = 0xff4fffff (–3.402823466e+38)
r20 = 1,
r40 = 0xff4fffff (–3.402823466e+38)
r45 = 0x7f800000 (+INF))
r50 = 0xbfc147ae (-1.51)
r60 = 0x00400000 (5.877471754e-39)
r70 = 0xffffffff (QNaN)
r80 = 0xffbfffff (SNaN)
The
The
The
[ IF rguard ] ifixieee rsrc1 → rdest
if rguard then {
}
rdest ← (long) ((float)rsrc1)
ifixieee
ifixieeeflags
ifixieee
Initial Values
operation. The update of the PCSW exception flags occurs at the same time as rdest is written. If any
operation converts the single-precision IEEE floating-point value in rsrc1 to a signed integer and
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
PRELIMINARY SPECIFICATION
operation computes the exception flags that would result from an individual
ifixieee r30 → r100
ifixieee r35 → r102
IF r10 ifixieee r40 → r105
IF r20 ifixieee r40 → r110
ifixieee r45 → r112
ifixieee r50 → r115
ifixieee r60 → r117
ifixieee r70 → r120
ifixieee r80 → r122
Convert floating-point to integer using PCSW
Operation
ifixieee
r100 ← 3
r102 ← 3, INX flag set
no change, since guard is false
r110 ← 0x80000000 (-2
r112 ← 0x7fffffff (2
r115 ← -2, INX flag set
r117 ← 0, IFZ set
r120 ← 0, INV flag set
r122 ← 0, INV flag set
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
ufixieee ifixrz ufixrz
Philips Semiconductors
causes an IEEE exception,
ATTRIBUTES
rounding mode
31
SEE ALSO
Result
-1), INV flag set
31
), INV flag set
ifixieee
121
1, 4
falu
No
—
1
3
.