EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 3
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
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Chapter Revision Dates .......................................................................... vii
About This Handbook .............................................................................. ix
Section I. Stratix Device Family Data Sheet
Chapter 1. Introduction
Chapter 2. Stratix Architecture
Altera Corporation
How to Find Information ........................................................................................................................ ix
How to Contact Altera ............................................................................................................................. ix
Typographic Conventions ........................................................................................................................ x
Revision History ............................................................................................................................ Part I–1
Introduction ............................................................................................................................................ 1–1
Features ................................................................................................................................................... 1–2
Functional Description .......................................................................................................................... 2–1
Logic Array Blocks ................................................................................................................................ 2–3
Logic Elements ....................................................................................................................................... 2–6
MultiTrack Interconnect ..................................................................................................................... 2–14
TriMatrix Memory ............................................................................................................................... 2–21
LAB Interconnects ............................................................................................................................ 2–4
LAB Control Signals ......................................................................................................................... 2–5
LUT Chain & Register Chain .......................................................................................................... 2–8
addnsub Signal ................................................................................................................................. 2–8
LE Operating Modes ........................................................................................................................ 2–8
Clear & Preset Logic Control ........................................................................................................ 2–13
Memory Modes ............................................................................................................................... 2–22
Clear Signals .................................................................................................................................... 2–24
Parity Bit Support ........................................................................................................................... 2–24
Shift Register Support .................................................................................................................... 2–25
Memory Block Size ......................................................................................................................... 2–26
Independent Clock Mode .............................................................................................................. 2–44
Input/Output Clock Mode ........................................................................................................... 2–46
Read/Write Clock Mode ............................................................................................................... 2–49
Single-Port Mode ............................................................................................................................ 2–51
Multiplier Block .............................................................................................................................. 2–57
Adder/Output Blocks ................................................................................................................... 2–61
Modes of Operation ....................................................................................................................... 2–64
Contents
iii
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