EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 401

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
June 2006
Interface Pins
RLDRAM II devices use interface pins such as data, clock, command, and
address pins. There are two types of RLDRAM II memory: common I/O
(CIO) and separate I/O (SIO). The data pins in RLDRAM II CIO device
are bidirectional while the data pins in a RLDRAM II SIO device are
uni-directional. Instead of bidirectional data strobes, RLDRAM II uses
differential free-running read and write clocks to accompany the data. As
in DDR SDRAM, data is sent and captured at twice the clock rate by
transferring data on both the positive and negative edge of a clock. The
commands and addresses still only use one active edge of a clock.
If the data pins are bidirectional, connect them to the Stratix and
Stratix GX device DQ pins. If the data pins are uni-directional, connect
the RLDRAM II device Q ports to the Stratix and Stratix GX device DQ
pins and connect the D ports to any user I/O pins in I/O banks 3, 4, 7, and
8. RLDRAM II also uses active-high data mask pins for writes. You can
connect DM pins to any of the I/O pins in the same bank as the DQ pins
of the FPGA. When interfacing with SIO devices, connect the DM pins to
any of the I/O pins in the same bank as the D pins. There is one DM pin
per DQS/DQ group.
Connect the read clock pins (QK) to Stratix and Stratix GX device DQS
pins. You must configure the DQS signals as bidirectional pins. However,
since QK pins are output-only pins from the memory, RLDRAM memory
interfacing in Stratix and Stratix GX devices requires that you ground the
DQS and DQSn pin output enables. The Stratix and Stratix GX devices
use the shifted QK signal from the DQS logic block to capture data. You
can leave the QK# signal of the RLDRAM II device unconnected.
RLDRAM II devices have both input clocks (CK and CK#) and write
clocks (DK and DK#). Use the external clock buffer to generate CK, CK#,
DK, and DK# to meet the CK, CK#, DK, and DK# skew requirements from
the RLDRAM II device. If you are interfacing with multiple RLDRAM II
devices, perform IBIS simulations to analyze the loading effects on the
clock pair.
You can use any of the user I/O pins for commands and addresses.
RLDRAM II also offers QVLD pins to indicate the read data availability.
Connect the QVLD pins to the Stratix and Stratix GX device DQVLD pins,
listed in the pin table.
Read & Write Operations
When reading from the RLDRAM II device, data is sent edge-aligned
with the read clock QK or QK# signal. When writing to the RLDRAM II
device, data must be center-aligned with the write clock (DK or DK#
signal). The Stratix and Stratix GX device RLDRAM II interface uses the
External Memory Interfaces in Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
3–5