EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 677
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
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Figure 9–5. Framer Transmitter Interface in Stratix & Stratix GX Devices
Altera Corporation
July 2005
Stratix & Stratix GX SFI-4 Transmitter
Stratix & Stratix GX
Logic Array
Fast PLL
8
8
Figure 9–6
interface implemented in Stratix and Stratix GX devices.
RXDATA[15..0] is received from the OC-192 SERDES on the differential
I/O pins of the Stratix or Stratix GX device. The receiver SERDES
converts the high-speed serial data to parallel. You can generate the
clocks required in the SERDES for parallel and serial data conversion
from the received RXCLK. RXCLK is inverted (phase-shifted by 180 ) to
capture received data. While normal I/O operation guarantees that data
is captured, it does not guarantee the parallelization boundary, which is
randomly determined based on the power up of both communicating
devices. The SERDES has embedded data realignment capability, which
can be used to save logic elements (LEs).
Stratix & Stratix GX SERDES
÷J
Register
Parallel
622 MHz
× W
shows the receiver block (from
Parallel-to-Serial
Register
W = 1
CH15
J = 8
CH0
Implementing SFI-4 in Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
TXCLK_SRC
TXDATA[15]
TXDATA[0]
622 Mbps
622 MHz
622MHz
TXCLK
Figure
9–4) of the SFI-4 framer
SERDES
OC-192
9–7
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