EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 679

IC STRATIX FPGA 20K LE 484-FBGA

EP1S20F484C6N

Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S20F484C6N

Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
Part Number:
EP1S20F484C6N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
0
Altera Corporation
July 2005
Tables 9–2
in Stratix and Stratix GX devices. See the High-Speed Differential I/O
Interfaces in Stratix Devices chapter in the Stratix Device Handbook or the
Stratix GX Device Handbook for the package type and the maximum
number of channels supported by each package.
Note to
(1)
Note to
(1)
EP1S10
EP1S20
EP1S25
EP1S30
EP1S40
EP1S60
EP1S80
EP1SGX10
EP1SGX25
EP1SGX40
Stratix Device
Table 9–2. Stratix SFI-4 Core Support
Table 9–3. Stratix GX SFI-4 Core Support
Stratix GX
Device
The LVDS channels can go up to 840 Mbps (or 1 Gbps using DPA in Stratix GX
devices). This number includes both high speed and low speed channels. The
high speed LVDS channels can go up to 840 Mbps. The low speed LVDS channels
can go up to 462 Mbps. The High-Speed Differential I/O Support chapters in the
Stratix Device Handbook, Volume 1 and the Stratix GX Device Handbook, Volume 1
and the device pin-outs on the web (www.altera.com) specify which channels are
high and low speed.
The LVDS channels can go up to 840 Mbps, or 1 Gbps using DPA. This number
includes both high speed and low speed channels. The high speed LVDS channels
can go up to 840 Mbps. The low speed LVDS channels can go up to 462 Mbps. The
High-Speed Differential I/O Support chapter in the Stratix Device Handbook, Volume
1 and the Stratix GX Device Handbook, Volume 1 and the device pin-outs on the web
(www.altera.com) specify which channels are high and low speed.
Table
Table
and
9–2:
9–3:
9–3
(Receiver/Transmitter)
(Receiver/Transmitter)
list the number of SFI-4 cores that can be implemented
Number of LVDS
Number of LVDS
Channels
Channels
116/116
152/156
44/44
66/66
78/78
82/82
90/90
22/22
39/39
45/45
Implementing SFI-4 in Stratix & Stratix GX Devices
(1)
(1)
Stratix Device Handbook, Volume 2
Number of PLLs
Number of PLLs
4
4
4
8
8
8
8
2
2
4
Number of SFI-4
Number of SFI-4
(Maximum)
(Maximum)
Interfaces
Interfaces
2
2
2
4
4
4
4
1
2
2
9–9

Related parts for EP1S20F484C6N