EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 638
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
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Arithmetic Functions
7–60
Stratix Device Handbook, Volume 2
This conversion is useful in different applications, such as position
control and position monitoring in robotics. It is also important to have
these transformations at very high speeds to accommodate real-time
processing.
Arithmetic Function Implementation
A common approach to implementing these arithmetic functions is using
the coordinate rotation digital computer (CORDIC) algorithm. The
CORDIC algorithm calculates the trigonometric functions of sine, cosine,
magnitude, and phase using an iterative process. It is made up of a series
of micro-rotations of the vector by a set of predetermined constants,
which are powers of 2.
Using binary arithmetic, this algorithm essentially replaces multipliers
with shift and add operations. In Stratix devices, it is possible to calculate
some of these arithmetic functions directly, without having to implement
the CORDIC algorithm.
This section describes a design example that calculates the magnitude of
a 9-bit signed vector (a,b) using a pipelined version of the square root
function available at the Altera IP Megastore. To calculate the sum of the
squares of the input (a
multipliers adder mode. The square root function is implemented using
an iterative algorithm similar to the long division operation. The binary
numbers are paired off, and subtracted by a trial number. Depending on
if the remainder is positive or negative, each bit of the square root is
determined and the process is repeated. This square root function does
not require memory and is implemented in logic cells only.
In this example, the input bit precision (IN_PREC) feeding into the square
root macro is set to twenty, and the output precision (OUT_PREC) is set to
ten. The number of precision bits is parameterizable. Also, there is a third
parameter, PIPELINE, which controls the architecture of the square root
macro. If this parameter is set to YES, it includes pipeline stages in the
square root macro. If set to NO, the square root macro becomes a single-
cycled combinatorial function.
Figure 7–38
Magnitude
Phase angle
shows the implementation the magnitude design.
m
= tan
=
2
a
+ b
-1
2
(b/a)
+
2
b
), configure the DSP block in the two-
2
Altera Corporation
September 2004
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