EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 342
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
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Fast PLLs
Figure 1–17. Stratix & Stratix GX Fast PLL Block Diagram
Notes to
(1)
(2)
(3)
1–32
Stratix Device Handbook, Volume 2
Global or
regional clock (1)
Clock
Input
The global or regional clock input can be driven by an output from another PLL or any dedicated CLK or FCLK pin.
It cannot be driven by internally-generated global signals.
In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES. Stratix and Stratix GX
devices only support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
This signal is a high-speed differential I/O support SERDES control signal.
Figure
1–17:
Frequency
Detector
general purpose abilities of the Fast PLL. For information on the high-
speed differential I/O interface capabilities, see the High-Speed Differential
I/O Interfaces in Stratix Devices chapter.
Phase
PFD
Charge
Pump
Loop
Filter
VCO Phase Selection
Selectable at each PLL
Output Port
÷m
VCO
8
Post-Scale
Counters
÷g0
÷l0
÷l1
Altera Corporation
diffioclk1 (2)
Global or
regional clock
txload_en (3)
rxload_en (3)
Global or
regional clock
diffioclk2 (2)
Global or
regional clock
July 2005
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