EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 518
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
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534
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Differential I/O Termination
Figure 5–32. Differential I/O Pin Locations
Differential I/O
Termination
5–46
Stratix Device Handbook, Volume 2
PCML, HyperTransport)
Differential I/O Pins
(LVDS, LVPECL,
f
Stratix devices implement differential on-chip termination to reduce
reflections and maintain signal integrity. On-chip termination also
minimizes the number of external resistors required. This simplifies
board design and places the resistors closer to the package, eliminating
small stubs that can still lead to reflections.
R
Stratix devices support differential on-chip termination for the LVDS I/O
standard. External termination is required on output pins for PCML
transmitters. HyperTransport, LVPECL, and LVDS receivers require
100 ohm termination at the input pins.
differential termination for the LVDS I/O standard.
For more information on differential on-chip termination technology, see
the Selectable I/O Standards in Stratix & Stratix GX Devices chapter.
AA
W
D
G
H
J
K
L
M
N
P
R
T
U
V
Y
A
B
C
D
E
F
Differential Termination
21
20
19
18
17
16
15
14
Regular I/O Pins
Regular I/O Pins
13
12
11
10
9
8
7
6
5
4
Figure 5–33
3
2
1
Differential I/O Pins
(LVDS, LVPECL,
PCML, HyperTransport)
shows the device with
Altera Corporation
July 2005
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