EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 4
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
- Current page: 4 of 864
- Download datasheet (11Mb)
Contents
Chapter 3. Configuration & Testing
Chapter 4. DC & Switching Characteristics
iv
PLLs & Clock Networks ..................................................................................................................... 2–73
I/O Structure ...................................................................................................................................... 2–104
High-Speed Differential I/O Support ............................................................................................ 2–130
Power Sequencing & Hot Socketing ............................................................................................... 2–140
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support ............................................................................ 3–1
SignalTap II Embedded Logic Analyzer ............................................................................................ 3–5
Configuration ......................................................................................................................................... 3–5
Stratix Automated Single Event Upset (SEU) Detection ................................................................ 3–12
Temperature Sensing Diode ............................................................................................................... 3–13
Operating Conditions ........................................................................................................................... 4–1
Power Consumption ........................................................................................................................... 4–17
Timing Model ....................................................................................................................................... 4–19
DSP Block Interface ........................................................................................................................ 2–70
Global & Hierarchical Clocking ................................................................................................... 2–73
Enhanced & Fast PLLs ................................................................................................................... 2–81
Enhanced PLLs ............................................................................................................................... 2–87
Fast PLLs ........................................................................................................................................ 2–100
Double-Data Rate I/O Pins ......................................................................................................... 2–111
External RAM Interfacing ........................................................................................................... 2–115
Programmable Drive Strength ................................................................................................... 2–119
Open-Drain Output ...................................................................................................................... 2–120
Slew-Rate Control ........................................................................................................................ 2–120
Bus Hold ........................................................................................................................................ 2–121
Programmable Pull-Up Resistor ................................................................................................ 2–122
Advanced I/O Standard Support .............................................................................................. 2–122
Differential On-Chip Termination ............................................................................................. 2–127
MultiVolt I/O Interface ............................................................................................................... 2–129
Dedicated Circuitry ...................................................................................................................... 2–137
Byte Alignment ............................................................................................................................. 2–140
Operating Modes .............................................................................................................................. 3–5
Configuring Stratix FPGAs with JRunner .................................................................................... 3–7
Configuration Schemes ................................................................................................................... 3–7
Partial Reconfiguration .................................................................................................................... 3–7
Remote Update Configuration Modes .......................................................................................... 3–8
Custom-Built Circuitry .................................................................................................................. 3–13
Software Interface ........................................................................................................................... 3–13
Preliminary & Final Timing .......................................................................................................... 4–19
Performance .................................................................................................................................... 4–20
Internal Timing Parameters .......................................................................................................... 4–22
External Timing Parameters ......................................................................................................... 4–33
Stratix External I/O Timing .......................................................................................................... 4–36
I/O Timing Measurement Methodology .................................................................................... 4–60
External I/O Delay Parameters .................................................................................................... 4–66
Stratix Device Handbook, Volume 1
Altera Corporation
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