EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 697

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
July 2005
updates the memory module for the Stratix or Stratix GX architecture and
instantiates the new synchronous memory megafunction, altsyncram,
which supports both RAM and ROM blocks in the Stratix and Stratix GX
architectures.
FIFO Conditions
First-in first-out (FIFO) functionality is slightly different in Stratix and
Stratix GX devices compared to APEX II and APEX 20K devices. Stratix
and Stratix GX devices do not support simultaneous reads and writes
from an empty FIFO buffer. Also, Stratix and Stratix GX devices do not
support the lpm_showahead parameter when targeting a FIFO buffer
because the TriMatrix memory blocks are synchronous. The
lpm_showahead parameter for APEX II and APEX 20K devices puts the
FIFO buffer in “read-acknowledge” mode so the first data written into the
FIFO buffer immediately flows through to the output. Other than these
two differences, all APEX II and APEX 20K FIFO functions are fully
compatible with the Stratix and Stratix GX architectures.
Design Migration Mode in Quartus II Software
The Quartus II software features a migration mode for simplifying the
process of converting APEX II and APEX 20K memory functions to the
Stratix or Stratix GX architecture. If the design can use the Stratix or
Stratix GX altsyncram megafunction as a replacement for a previous
APEX II or APEX 20K memory function while maintaining functionally
similar behavior, the Quartus II software automatically converts the
memory. The software produces a warning message during compilation
reminding you to verify that the design migrated correctly.
For memory blocks with all inputs registered, the existing megafunction
is converted to the new altsyncram megafunction. The software
generates a warning when the altsyncram megafunction is
incompatible. For example, a RAM block with all inputs registered except
the read enable compiles with a warning message indicating that the
read-enable port is registered.
You can suppress warning messages for the entire project or for
individual memory blocks by setting the
SUPPRESS_MEMORY_CONVERSION_WARNINGS parameter to “on” as a
global parameter by selecting Assignment Organizer (Tools menu). In
the Assignment Organizer window, click Parameters in the Assignment
Categories box. Type SUPPRESS_MEMORY_CONVERSION_WARNINGS in
the Assignment Name box and type ON in the Assignment Setting box.
To suppress these warning messages on a per-memory-instance basis, set
the SUPPRESS_MEMORY_CONVERSION_WARNINGS parameter in the
Assignment Organizer to “on” for the memory instance.
Transitioning APEX Designs to Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
10–13