EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 775
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
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Altera Corporation
July 2005
nRS
RDYnBSY
Table 11–15. Dedicated Configuration Pins on the Stratix or Stratix GX Device
Pin Name
I/O
I/O
User Mode
PPA
PPA
Configuration
Scheme
Input
Output
Pin Type
Read strobe input. A low input directs the
device to drive the
DATA7
If the
should be tied high. In non-PPA schemes, it
functions as a user I/O during configuration,
which means it is tri-stated.
After PPA configuration,
user I/O and the state of this pin depends on
the Dual-Purpose Pin settings.
Ready output. A high output indicates that the
target device is ready to accept another data
byte. A low output indicates that the target
device is busy and not ready to receive another
data byte.
In PPA configuration schemes, this pin drives
out high after power-up, before configuration
and after configuration before entering user-
mode. In non-PPA schemes, it functions as a
user I/O during configuration, which means it is
tri-stated.
After PPA configuration,
as a user I/O and the state of this pin depends
on the Dual-Purpose Pin settings.
Configuring Stratix & Stratix GX Devices
nRS
pin.
Stratix Device Handbook, Volume 2
pin is not used in PPA mode, it
Description
RDYnBSY
(Part 7 of 8)
RDYnBSY
nRS
is available as a
signal on the
is available
11–57
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