EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 378
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
- Current page: 378 of 864
- Download datasheet (11Mb)
Using TriMatrix Memory
2–10
Stratix Device Handbook, Volume 2
128
512
256
128
64K
32K
16K
8K
4K
Table 2–8. M4K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 2 of 2)
Table 2–9. M-RAM Block Mixed-Width Configurations (Simple Dual-Port Mode)
Read Port
72
144
32
9
18
36
9
18
36
Read Port
4K
f
v
1 2K
v
M512 blocks support serializer and deserializer (SERDES) applications.
By using the mixed-width support in combination with double data rate
(DDR) I/O standards, the block can function as a SERDES to support low-
speed serial I/O standards using global or regional clocks.
For more information on Stratix device I/O structure see the Stratix
Device Family Data Sheet section of the Stratix Device Handbook, Volume 1.
For more information on Stratix GX device I/O structure see the
Stratix GX Device Family Data Sheet section of the Stratix GX Device
Handbook, Volume 1.
In simple dual-port mode, the M512 and M4K blocks have one write
enable and one read enable signal. The M512 does not support a clear port
on the rden register. On the M4K block, asserting the clear port of the
rden register drives rden high, which allows the read operation to occur.
When the read enable is deactivated, the current data is retained at the
output ports. If the read enable is activated during a write operation with
the same address location selected, the simple dual-port RAM output is
either unknown or can be set to output the old data stored at the memory
address. For more information, see
Same Address” on page
2 1K
64K
v
v
v
v
v
4 512
9
v
32K
8 256
v
v
v
v
18
2–25.
Write Port
v
16 128
Write Port
16K
“Read-During-Write Operation at the
v
v
v
v
v
36
32 512
v
v
v
8K
9 256
v
v
v
v
72
Altera Corporation
v
v
v
18 128
4K
July 2005
v
v
v
v
144
36
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