EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 747
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
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Figure 11–15. Timing Waveform for Configuring Devices in FPP Mode
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
July 2005
t
t
t
t
t
t
t
CF2CK
DSU
DH
CFG
CH
CL
CLK
Table 11–9. FPP Timing Parameters for Stratix & Stratix GX Devices (Part 1 of 2)
Symbol
The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Upon power-up, the Stratix II device holds nSTATUS low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
DCLK should not be left floating after configuration. It should be driven high or low, whichever is convenient.
DATA[] is available as user I/Os after configuration and the state of these pins depends on the dual-purpose pin
settings.
CONF_DONE (3)
Figure
nSTATUS (2)
nCONFIG
Data setup time before rising edge on
Data hold time after rising edge on
nCONFIG
DCLK
DCLK
DCLK
INIT_DONE
DATA[7..0}
nCONFIG
11–15:
User I/O
DCLK
high time
low time
period
high to first rising edge on
low pulse width
t
t
CF2CD
CFG
FPP Configuration Timing
Figure 11–15
Stratix GX device in FPP mode.
parameters for Stratix or Stratix GX devices.
t
CF2ST1
t
CF2ST0
t
CF2CK
t
ST2CK
Parameter
t
Byte 0 Byte 1 Byte 2 Byte 3
STATUS
High-Z
t
CH
t
CLK
t
DSU
t
CL
t
DH
shows FPP timing waveforms for configuring a Stratix or
DCLK
DCLK
DCLK
Table 11–9
Byte n
Configuring Stratix & Stratix GX Devices
Note (1)
Stratix Device Handbook, Volume 2
Min
40
40
10
7
0
4
4
shows the FPP timing
t
CD2UM
Max
User Mode
User Mode
(4)
(4)
Units
µs
ns
ns
µs
ns
ns
ns
11–29
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