EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 469
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
- Current page: 469 of 864
- Download datasheet (11Mb)
Figure 4–24. Floorplan View Window
Altera Corporation
June 2006
Auto Placement & Verification of Selectable I/O Standards
The Quartus II software automatically verifies the placement for all I/O
and V
■
■
■
■
■
Automatically places I/O pins of different V
pin assignments in separate I/O banks and enables the V
these I/O banks.
Verifies that voltage-referenced I/O pins requiring different V
levels are not placed in the same bank.
Reports an error message if the current limit is exceeded for a Stratix
or Stratix GX power bank, as determined by the equation
documented in
Reserves the unused high-speed differential I/O channels and
regular user I/O pins in the high-speed differential I/O banks when
any of the high-speed differential I/O channels are being used.
Automatically assigns V
requirements are met and I/O standards are placed properly.
REF
pins and performs the following actions.
Selectable I/O Standards in Stratix & Stratix GX Devices
“DC Guidelines” on page
REF
pins and I/O pins such that the current
Stratix Device Handbook, Volume 2
4–35.
REF
standards without
REF
pins of
REF
4–41
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