EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 742
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Configuration Schemes
11–24
Stratix Device Handbook, Volume 2
Do not drive CONF_DONE low after device configuration to delay
initialization. Instead, use the Enable User-Supplied Start-Up Clock
(CLKUSR) option in the Device & Pin Options dialog box. You can use
this option to synchronize the initialization of multiple devices that are
not in the same configuration chain. Devices in the same configuration
chain initialize together.
After the first Stratix or Stratix GX device completes configuration during
multi-device configuration, its nCEO pin activates the second Stratix or
Stratix GX device’s nCE pin, prompting the second device to begin
configuration. Because CONF_DONE pins are tied together, all devices
initialize and enter user mode at the same time. Because nSTATUS pins
are tied together, configuration stops for the whole chain if any device
(including enhanced configuration devices) detects an error. Also, if the
enhanced configuration device does not detect a high on CONF_DONE at
the end of configuration, it pulses its OE low for a few microseconds to
reset the chain. The low OE pulse drives nSTATUS low on all Stratix and
Stratix GX devices, causing them to enter an error state. This state is
similar to a Stratix or Stratix GX device detecting an error.
If the Auto-restart configuration after error option is on, the Stratix and
Stratix GX devices release their nSTATUS pins after a reset time-out
period. When the nSTATUS pins are released and pulled high, the
configuration device reconfigures the chain. If the Auto-restart
configuration after error option is off, nSTATUS stays low until the
Stratix and Stratix GX devices are reset with a low pulse on nCONFIG.
Figure 11–11
timing waveform for Stratix and Stratix GX devices.
shows the FPP configuration with a configuration device
Altera Corporation
July 2005
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