EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 674
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
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Introduction
9–4
Stratix Device Handbook, Volume 2
Figure 9–3. SFI-4 Interface Signals
The framer transmits outbound data via TXDATA[15..0] and is
received at the SERDES using TXCLK. TXCLK is derived from
TXCLK_SRC, which is provided by the OC-192 SERDES. The framer
receives incoming data on RXDATA[15..0] from the OC-192 SERDES.
The data received is latched on the rising edge of RXCLK.
provides the data rates and clock frequencies specified by SFI-4. The
modes of TXCLK are specified by the SFI-4 standard. In required mode
(622 MHz clock mode or 1 mode), TXCLK should run at 622.08 MHz. In
optional mode (311 MHz clock mode or 2 mode), TXCLK should run at
311.04 MHz.
TXDATA[15..0]
TXCLK
TXCLK_SRC
RXDATA[15..0]
RXCLK
REFCLK
Table 9–1. SFI-4 Interface Data Rates & Clock Frequencies
SONET Framer
SONET Framer
Transmitter
Receiver
Signal
TXDATA[15..0]
RXDATA[15..0]
TXCLK_SRC
RXCLK
TXCLK
622.08 Mbps
622.08 MHz or 311.04 MHz
622.08 MHz
622.08 Mbps
622.08 MHz
622.08 MHz
REFCLK
Performance
OC-192 SERDES
Recovered Clock
Transmitter
Receiver
Altera Corporation
Table 9–1
July 2005
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