EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 421
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
- Current page: 421 of 864
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Altera Corporation
June 2006
The Stratix and Stratix GX DDR IOE structure requires you to invert the
incoming DQS signal by using a NOT gate to ensure proper data transfer.
The altdq megafunction automatically adds the inverter when it
generates the DQ signals. As shown in
rising edge clocks the A
the B
memory read operation, the last data coincides with DQS being low. If
you do not invert the DQS pin, you do not get this last data because the
latch does not open until the next rising edge of the DQS signal. The NOT
gate is inserted automatically if the altdg megafunction is used;
otherwise you need to add the NOT gate manually.
Figure 3–14
second set of waveforms in
shifted DQS signal is not inverted; the last data, D
into the logic array as DQS goes to tristate after the read postamble time.
The third set of waveforms in
with the DQS signal inverted after the 90° shift; the last data D
latched. In this case the outputs of register A
correspond to dataout_h and dataout_l ports, are now switched
because of the DQS inversion.
I
register, and latch C
shows waveforms of the circuit shown in
External Memory Interfaces in Stratix & Stratix GX Devices
I
register, inclock signal's falling edge clocks
I
is opened when inclock is one. In a DDR
Figure 3–14
Figure 3–14
Figure
Stratix Device Handbook, Volume 2
shows what happens if the
shows a proper read operation
I
3–10, the inclock signal's
and latch C
n
, does not get latched
Figure
I
, which
3–12. The
n
does get
3–25
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