EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 614

IC STRATIX FPGA 20K LE 484-FBGA

EP1S20F484C6N

Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S20F484C6N

Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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0
Infinite Impulse Response (IIR) Filters
7–36
Stratix Device Handbook, Volume 2
This cascaded structure rearranges the transfer function. This is shown in
the equation below, where each product term is a second order IIR filter.
If n is odd, the last product term is a first order IIR filter:
Figure 7–21
Figure 7–21. Cascaded IIR Filter
Basic IIR Filters
In this section, the basic IIR filter is implemented using cascaded second
order blocks or biquads in the direct form II structure.
Basic IIR FIlter Implementation
Multiplier blocks, adders and delay elements can implement a basic IIR
filter. The Stratix architecture lends itself to IIR filters because of its
embedded DSP blocks, which can easily be configured to perform these
operations. The altmult_add megafunction can be used to implement
the multiplier-adder mode in the DSP blocks.
implementation of an individual biquad using Stratix and Stratix GX DSP
blocks.
H z
x(n)
=
shows the cascaded structure.
C
C
n
H (z)
+
k
1
1
=
1
2
a
--------------------------------------------------- -
1
0k
+
+
b
a
1k
1k
z
z
1 –
H (z)
1 –
k
+
+
b
a
2k
2k
z
z
2 –
2 –
Figure 7–22
=
C
H (z)
n
n
Altera Corporation
+
k
1
=
September 2004
shows the
1
2
H
y(n)
k
z

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