EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 503

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Figure 5–23. Bit Orientation in the Quartus II Software
Figure 5–24. Bit Order for One Channel of Differential Data
Altera Corporation
July 2005
high-frequency clock
Example: Sending the Data 10010110
Data in/
Data out
Data in/
Data out
inclock/outclock
inclock/outclock
data in
Previous Cycle
Previous Cycle
Differential I/O Bit Position
Data synchronization is necessary for successful data transmission at
high frequencies.
channel operating in
significant bits (MSBs) and least significant bits (LSBs) after
deserialization, as listed in
n-1
n-0
MSB
MSB
D7
1
MSB
9
D6
Figure 5–24
0
High-Speed Differential I/O Interfaces in Stratix Devices
8
×
D5
0
8 mode. Similar positioning exists for the most
7
Current Cycle
Current Cycle
D4
1
Table
6
shows the data bit orientation for a receiver
D3
0
10 LVDS Bits
5–5.
5
D2
1
4
Stratix Device Handbook, Volume 2
D1
1
3
LSB
LSB
D0
0
2
1
Next Cycle
Next Cycle
LSB
0
5–31