EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 151

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
Figure 5–37. Scan Chain Order of PLL Components for Arria II GX PLLs
Figure 5–38. Scan Chain Order of PLL Components for Top and Bottom of Arria II GZ PLLs
Note to
(1) Left and right PLLs have the same scan chain order. The post-scale counters end at C6.
Figure 5–39. Scan Chain Bit-Order Sequence for Post-Scale Counters in Arria II PLLs
December 2010 Altera Corporation
Figure
DATAOUT
5–39:
DATAIN
DATAIN
HB
LB
0
0
Figure 5–37
seven post-scale counters. The reconfiguration bits start with the C6 post-scale
counter.
Figure 5–38
Arria II GZ PLLs.
Figure 5–39
Arria II PLLs.
HB
C6
C6
C7
LB
1
1
MSB
MSB
DATAOUT
shows the scan chain order of Arria II GX PLL components which have
shows the scan chain order of PLL components for the top and bottom
shows the scan chain bit-order sequence for post-scale counters in all
HB
LB
LF
2
LF
2
C8
C5
C5
K
K
HB
LB
3
3
CP
CP
C9
HB
C4
C4
LB
LSB
4
4
LSB
Arria II Device Handbook Volume 1: Device Interfaces and Integration
HB
LB
5
5
DATAOUT
C3
C3
N
N
HB
LB
6
6
HB
LB
C2
C2
7
7
M
M
(Note 1)
rselodd
rbypass
C1
C1
C0
C0
DATAIN
5–47