EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 504

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–14
Figure 2–7. Transmitter Datapath Clocking in a ×8 Bonded Configuration
Note to
(1) In Arria II GX and GZ devices, there is only one dedicated PCIe hard IP, which supports PCIe Gen 1 ×1, ×4, and ×8; and PCIe Gen 2 (Arria II GZ
Arria II Device Handbook Volume 2: Transceivers
Fabric
FPGA
only) ×1 and ×4.
Figure
2–7:
hard IP
hard IP
PCIe
PCIe
1
(1)
coreclkout
Figure 2–7
configurations.
Figure 2–8
locations and PCIe logical lane-to-physical transceiver channel mapping in all
Arria II GX and GZ devices.
The Quartus II Compiler generates an error if you do not map the PCIe logical lanes to
the physical transceiver channels, as shown in
Master Transceiver Block
Slave Transceiver Block
Interface
Interface
PIPE
PIPE
shows transmitter datapath clocking in PCIe ×8 channel bonding
through
Channel3
Channel3
Input Reference Clock
Input Reference Clock
Compensation
Compensation
wrclk
wrclk
/2
TX Phase
TX Phase
FIFO
FIFO
Figure 2–10
rdclk
rdclk
CMU1_PLL
CMU0_PLL
wrclk
wrclk
Byte Serializer
Byte Serializer
show allowed master and slave transceiver block
Transmitter Channel PCS
/2
Transmitter Channel PCS
/2
rdclk
rdclk
CMU1_PLL
CMU0_PLL
Figure 2–8
Chapter 2: Transceiver Clocking in Arria II Devices
CMU1 Clock Divider
CMU0 Clock Divider
8B/10B Encoder
8B/10B Encoder
CMU1 Clock Divider
CMU0 Clock Divider
From CMU0 of the Master
From CMU0 of the Master
Transceiver Block
Transceiver Block
CMU1_Channel
CMU0_Channel
CMU1_Channel
CMU0_Channel
through
Transceiver Channel Datapath Clocking
December 2010 Altera Corporation
FPGA Fabric-Transceiver Interface Clock
High-Speed Serial Clock
Low-Speed Parallel Clock
Figure
Transmitter Channel
Transmitter Channel
2–10.
PMA
PMA