EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 20

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–6
Arria II Device Architecture
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Arria II devices include a customer-defined feature set optimized for cost-sensitive
applications and offer a wide range of density, memory, embedded multiplier, I/O,
and packaging options. Arria II devices support external memory interfaces and I/O
protocols required by wireless, wireline, broadcast, computer, storage, and military
markets. They inherit the 8-input ALM, M9K and M144K embedded RAM block, and
high-performance DSP blocks from the Stratix
cost-optimized I/O cell and a transceiver optimized for 6.375 Gbps speeds.
Figure 1–1
architecture, respectively.
Figure 1–1. Architecture Overview for Arria II GX Devices
Transceiver
PLL
Blocks
and
PLL
DLL
Figure 1–2
High-Speed Differential I/O,
High-Speed Differential I/O,
General Purpose I/O, and
General Purpose I/O, and
Plug and Play PCIe hard IP
All the blocks in this graphic are for the largest density in the
× ×
Memory Interface
Arria II GX family. The number of blocks can vary based on
Memory Interface
1, 2, ×4, and ×8
show an overview of the Arria II GX and Arria II GZ device
Embedded Memory, Clock Networks)
the density of the device.
(Logic Elements, DSP,
Arria II GX FPGA Fabric
®
High-Speed Differential I/O,
High-Speed Differential I/O,
General Purpose I/O, and
General Purpose I/O, and
IV device family with a
Chapter 1: Overview for the Arria II Device Family
Memory Interface
Memory Interface
December 2010 Altera Corporation
Arria II Device Architecture
Differential I/O
Differential I/O
High-Speed
High-Speed
DLL
with DPA,
Purpose
Interface
with DPA,
Purpose
General
I/O, and
Memory
Interface
General
Memory
I/O, and
PLL
PLL
PLL
PLL