EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 326

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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Configuration Data Decompression
Arria II Device Handbook Volume 1: Device Interfaces and Integration
1
1
Arria II devices support configuration data decompression, which saves
configuration memory space and time. This feature allows you to store compressed
configuration data in configuration devices or other memory and transmit this
compressed bitstream to Arria II devices. During configuration, the Arria II device
decompresses the bitstream in real time and programs its SRAM cells.
Preliminary data indicates that compression typically reduces the configuration
bitstream size by 35 to 55% based on the designs used.
Arria II devices support decompression in the FPP (when using a MAX II device or
microprocessor + flash), AS or fast AS, and PS configuration schemes. The Arria II
device decompression feature is not available in the JTAG configuration scheme.
When using FPP mode, the intelligent host must provide a DCLK that is ×4 the data
rate. Therefore, the configuration data must be valid for four DCLK cycles.
In PS mode, use the Arria II decompression feature because sending compressed
configuration data reduces configuration time.
When you enable compression, the Quartus II software generates configuration files
with compressed configuration data. This compressed file reduces the storage
requirements in the configuration device or flash memory and decreases the time
needed to transmit the bitstream to the Arria II device. The time required by an
Arria II device to decompress a configuration file is less than the time needed to
transmit the configuration data to the device.
There are two ways to enable compression for Arria II bitstreams—before design
compilation (in the Compiler Settings menu) and after design compilation (in the
Convert Programming Files window).
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
December 2010 Altera Corporation
Configuration Data Decompression