EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 99

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EP2AGX95EF29C4N

Manufacturer Part Number
EP2AGX95EF29C4N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr

Specifications of EP2AGX95EF29C4N

Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2AGX95EF29C4N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2AGX95EF29C4N
Manufacturer:
ALTERA
0
Part Number:
EP2AGX95EF29C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 4: DSP Blocks in Arria II Devices
Arria II Operational Mode Descriptions
Figure 4–19. Shift Operation Mode Shown for Half-DSP Block
Table 4–5. Examples of Shift Operations
December 2010 Altera Corporation
Arithmetic Shift Right
Arithmetic Shift Left
Logical Shift Right
Logical Shift Left
Rotation ROT[N]
LSR[32-N]
ASR[32-N]
Example
LSL[N]
ASL[N]
dataa_0[35..18]
datab_0[35..18]
datab_0[35..18]
dataa_0[35..18]
dataa_0[17..0]
datab_0[17..0]
dataa_0[17..0]
datab_0[17..0]
Figure 4–19
Table 4–5
Unsigned
Unsigned
Unsigned
Signed
Signed
Signa
Half-DSP Block
clock[3..0]
lists examples of shift operations.
aclr[3..0]
ena[3..0]
shows the shift mode configuration.
Unsigned
Unsigned
Unsigned
Unsigned
Unsigned
Signb
Shift
0
1
0
1
0
+
+
shift_right
rotate
signa
signb
Rotate
0
0
0
0
1
Arria II Device Handbook Volume 1: Device Interfaces and Integration
+
0×AABBCCDD
0×AABBCCDD
0×AABBCCDD
0×AABBCCDD
0×AABBCCDD
A-input
0×0000100
0×0000100
0×0000100
0×0000100
0×0000100
B-input
32
result[ ]
0×BBCCDDAA
0×BBCCDD00
0×BBCCDD00
0×000000AA
0×FFFFFFAA
Result
4–27

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