EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 543

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface Clocking
Table 2–13. Receiver Phase Compensation FIFO Write Clocks for Arria II Devices
December 2010 Altera Corporation
Non-Bonded Channel Configuration
with rate matcher
Non-Bonded Channel Configuration
without rate matcher
×4 Bonded Channel Configuration
×8 Bonded Channel Configuration
Configuration
1
1
Table 2–13
software selects in various configurations.
To ensure that you understand the 0 PPM clock driver rule, the Quartus II software
expects the “GXB 0 PPM Core Clock Setting” user assignment whenever you use the
rx_coreclk port to drive the receiver phase compensation FIFO read clock.
Failing to make this assignment correctly when using the rx_coreclk port results in a
Quartus II compilation error.
GXB 0 PPM Core Clock Setting
The GXB 0 PPM core clock setting is intended for advanced users who know the
clocking configuration of the entire system and want to reduce the FPGA fabric global
and regional clock resource utilization. The GXB 0 PPM core clock setting allows the
following clock drivers to drive the rx_coreclk ports:
■
■
■
■
■
■
The Quartus II software does not allow gated clocks or clocks generated in FPGA
logic to drive the tx_coreclk ports.
tx_clkout in non-bonded channel configurations with rate matcher
tx_clkout and rx_clkout in non-bonded configurations without rate matcher
coreclkout in bonded channel configurations
FPGA CLK input pins
Transceiver REFCLK pins
Clock output from the left corner PLLs (PLL_1 and PLL_4)
lists the receiver phase compensation FIFO write clocks that the Quartus II
Low-speed parallel clock from the local
clock divider in the associated channel
(tx_clkout)
Parallel recovered clock from the
receiver PMA in the associated channel
(rx_clkout)
Low-speed parallel clock from the CMU0
clock divider of the associated
transceiver block (coreclkout)
Low-speed parallel clock from the CMU0
clock divider of the master transceiver
block (coreclkout from the master
transceiver block)
Without Byte Deserializer
Receiver Phase Compensation FIFO Write Clock
Arria II Device Handbook Volume 2: Transceivers
Divide-by-two version of the low-speed
parallel clock from the local clock
divider in the associated channel
(tx_clkout)
Divide-by-two version of the parallel
recovered clock from the receiver PMA
in the associated channel (rx_clkout)
Divide-by-two version of the low-speed
parallel clock from the CMU0 clock
divider of the associated transceiver
block (coreclkout)
Divide-by-two version of the low-speed
parallel clock from the CMU0 clock
divider of the master transceiver block
(coreclkout from the master
transceiver block)
With Byte Deserializer
2–53