EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 477

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Dynamic Reconfiguration
Table 1–22. Patterns in PRBS Mode for Arria II Devices (Part 2 of 2)
Dynamic Reconfiguration
December 2010 Altera Corporation
Notes to
(1) A verifier is not available for the specified patterns.
High frequency
Low frequency
Patterns
Table
1–22:
f
1
(1)
(1)
1010101010
0000011111
Figure 1–87
pattern verifier.
Figure 1–87. Input and Output Ports for the BIST and PRBS Modes
Notes to
(1) rx_serilalpbken is optional.
(2) The rx_bisterr and rx_bistdone signals are not available when using only the high-frequency and low-frequency
You can reset the PRBS pattern generator and verifier by asserting the
tx_digitalreset and rx_digitalreset signals, respectively.
rx_digitalreset does not reset the BIST output signals when the following
conditions are true:
■
■
Dynamic reconfiguration allows you to reconfigure the transceiver block without
reconfiguring the FPGA. For hot-plug or open-standard systems, this feature allows
you to support multiple data rates or standards without reconfiguring the system. For
all systems, it allows you to make changes to the bit error rate to compensate
in-system for the effects of process and temperature.
For more information, refer to
Arria II
Polynomial
pll_powerdown is high in BIST mode
pll_powerdown or rx_analogreset is high in PRBS mode
pattern generator. The rx_bistdone port is asserted and stays high when the verifier either receives one full cycle
of incremental pattern or detects an error in the receiver data. The rx_bisterr signal is asserted and stays high
when the verifier detects an error.
Figure
Devices.
shows the enabled input and output ports of the pattern generator and
1–87:
Channel Width
of 8-Bit
8 or 10 bit
tx_seriallpbken[ ] (1)
10 bit
tx_digitalreset
rx_digitalreset
(1)
tx_datain[ ]
pll_inclk
Word Alignment
AN 558: Implementing Dynamic Reconfiguration in
Pattern
NA
NA
and Pattern Verifier
Pattern Generator
2.5 for 8-bit pattern and 3.125 for 10-bit pattern
Arria II Device Handbook Volume 2: Transceivers
Maximum Data Rate
tx_dataout
rx_bisterr (2)
rx_bistdone (2)
3.125
1–91