EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 267

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Pin Placement Guidelines
Differential Pin Placement Guidelines
December 2010 Altera Corporation
DPA-Enabled Channels and Single-Ended I/Os
Guidelines for DPA-Enabled Differential Channels
1
To ensure proper high-speed operation, differential pin placement guidelines are
established. The Quartus II Compiler automatically checks that these guidelines are
followed and issues an error message if they are not adhered to.
DPA-enabled differential channels refer to DPA mode or soft CDR mode;
DPA-disabled channels refer to non-DPA mode.
When single-ended I/Os and LVDS I/Os share the same I/O bank, the placement of
single-ended I/O pins with respect to LVDS I/O pins is restricted. The constraints on
single-ended I/Os placement with respect to DPA-enabled or DPA-disabled LVDS
I/Os are the same.
■
■
■
When you use DPA-enabled channels, you must adhere to the guidelines listed in the
following sections.
DPA-Enabled Channel Driving Distance
If the number of DPA-enabled channels driven by each center or corner PLL exceeds
25 LAB rows, Altera recommends implementing data realignment (bit slip) circuitry
for all the DPA channels.
Using Center and Corner Left and Right PLLs in Arria II GX Devices
If the DPA-enabled channels in a bank are being driven by two PLLs, where the corner
PLL is driving one group and the center PLL is driving another group, there must be
at least one row of separation between the two groups of DPA-enabled channels, as
shown in
can operate at independent frequencies.
Single-ended I/Os are allowed in the same I/O bank, if the single-ended I/O
standard uses the same V
Single-ended inputs can be in the same logic array block (LAB) row as a
differential channel using the SERDES circuitry.
Double data rate I/O (DDIO) can be placed within the same LAB row as a SERDES
differential channel but half rate DDIO or single data rate (SDR) output pins
cannot be placed within the same LAB row as a receiver SERDES differential
channel. The input register must be implemented within the FPGA fabric logic.
Figure
8–23. This separation prevents noise mixing because the two groups
CCIO
as the DPA-enabled differential I/O bank.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
8–27