EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 523
EP2AGX95EF29C4N
Manufacturer Part Number
EP2AGX95EF29C4N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29C4N.pdf
(306 pages)
Specifications of EP2AGX95EF29C4N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2AGX95EF29C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP2AGX45CU17C6N PDF datasheet
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- EP2AGX95EF29C4N PDF datasheet #6
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Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface Clocking
Figure 2–19. FPGA Fabric-Transmitter Interface Clocking for Example 2
December 2010 Altera Corporation
Channel PMA
Channel PMA
Channel PMA
Channel PMA
Transceiver
Transceiver
Transceiver
Transceiver
Divider Block
Divider Block
Divider Block
Divider Block
Local Clock
Local Clock
Local Clock
Local Clock
Channel 3
Channel 2
Channel 1
Channel 0
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Transmitter Channel PCS
Transmitter Channel PCS
CMU1 Block
CMU0 Block
Transmitter Channel PCS
Transmitter Channel PCS
Figure 2–19
Divider
Divider
CMU1
CMU0
Clock
Clock
shows FPGA fabric-transmitter interface clocking for Example 2.
/2
/2
/2
/2
CMU1
CMU0
PLL
PLL
Compensation
Compensation
Compensation
Compensation
rdclk
rdclk
rdclk
rdclk
TX Phase
TX Phase
TX Phase
TX Phase
Input Reference Clock
Input Reference Clock
FIFO
FIFO
FIFO
FIFO
wrclk
wrclk
wrclk
wrclk
tx_clkout[2]
tx_clkout[0]
Arria II Device Handbook Volume 2: Transceivers
FPGA Fabric
tx_coreclk[3]
tx_coreclk[2]
tx_coreclk[1]
tx_coreclk[0]
and Control
and Control
and Control
and Control
Channel 3
Channel 2
Channel 1
Channel 0
TX Data
TX Data
TX Data
TX Data
Logic
Logic
Logic
Logic
2–33
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