EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 317

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EP2AGX95EF29C4N

Manufacturer Part Number
EP2AGX95EF29C4N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr

Specifications of EP2AGX95EF29C4N

Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

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Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
JTAG Configuration
December 2010 Altera Corporation
f
f
1
1
You must connect the nCE pin to GND or drive it low during JTAG configuration. In
multi-device FPP, AS, and PS configuration chains, the nCE pin of the first device is
connected to GND, while its nCEO pin is connected to nCE of the next device in the
chain. The nCE input of the last device comes from the previous device, while its nCEO
pin is left floating. In addition, the CONF_DONE and nSTATUS signals are all shared in
multi-device FPP, AS, or PS configuration chains so the devices can enter user mode at
the same time after configuration is complete. When the CONF_DONE and nSTATUS
signals are shared among all the devices, you must configure every device when JTAG
configuration is performed.
If you only use JTAG configuration, Altera recommends connecting the circuitry as
shown in
enable each device to enter user mode individually.
After the first device completes configuration in a multi-device configuration chain,
its nCEO pin drives low to activate the nCE pin of the second device, which prompts the
second device to begin configuration. Therefore, if these devices are also in a JTAG
chain, ensure the nCE pins are connected to GND during JTAG configuration or that
the devices are JTAG configured in the same order as the configuration chain. As long
as the devices are JTAG configured in the same order as the multi-device
configuration chain, the nCEO of the previous device drives the nCE of the next device
low when it has successfully been JTAG configured.
You can place other Altera devices that have JTAG support in the same JTAG chain for
device programming and configuration.
JTAG configuration support is enhanced and allows more than 17 Arria II devices to
be cascaded in a JTAG chain.
For more information about configuring multiple Altera devices in the same
configuration chain, refer to the
volume 2 of the Configuration Handbook.
You can configure Arria II devices using multiple configuration schemes on the same
board. Combining JTAG configuration with a PS or AS configuration on your board is
useful in the prototyping environment because it allows multiple methods to
configure your FPGA.
For more information about combining JTAG configuration with other configuration
schemes, refer to the
the Configuration Handbook.
Figure
9–17, where each of the CONF_DONE and nSTATUS signals are isolated to
Combining Different Configuration Schemes
Configuring Mixed Altera Device Chains
Arria II Device Handbook Volume 1: Device Interfaces and Integration
chapter in volume 2 of
chapter in
9–37

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