EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 491

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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AIIGX52002-3.0
CMU PLL and Receiver CDR Input Reference Clocking
Arria II Device Handbook Volume 2: Transceivers
December 2010
December 2010
AIIGX52002-3.0
This chapter describes the Arria
including the input reference clocking, transceiver channel datapath clocking, FPGA
fabric-transceiver interface clocking, and FPGA fabric phase-locked loop
(PLL)-transceiver PLL cascading.
This chapter includes the following sections:
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Each transceiver block in the Arria II GX and GZ device contains the following:
■
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The CMU PLLs and receiver CDRs require an input reference clock to operate. The
CMU PLL synthesizes the input reference clock to generate the high-speed serial clock
used in the transmitter physical media attachment (PMA). The receiver CDR uses the
input reference clock as a training clock when it is in lock-to-reference (LTR) mode.
The CMU PLLs and receiver CDRs in each transceiver block can derive input
reference from one of the following sources:
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■
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“CMU PLL and Receiver CDR Input Reference Clocking”
“Transceiver Channel Datapath Clocking” on page 2–6
“FPGA Fabric-Transceiver Interface Clocking” on page 2–28
“FPGA Fabric PLL-Transceiver PLL Cascading” on page 2–56
“Using the CMU PLL for Clocking User Logic in the FPGA Fabric” on page 2–66
Two clock multiplier unit (CMU) PLLs (CMU0 PLL and CMU1 PLL)
Four clock data recovery (CDR) units, one in each receiver channel
refclk0 and refclk1 pins of the same transceiver block
refclk0 and refclk1 pins of other transceiver blocks on the same side of the
device using the inter-transceiver block (ITB) clock network
Dedicated CLK input pins on the FPGA global clock network
Clock output pins from the left-side PLLs (PLL_1 and PLL_4) in the FPGA fabric
2. Transceiver Clocking in Arria II
®
II GX and GZ transceiver clocking architecture,
Devices
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