EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 308

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–28
Figure 9–12. Multiple-Device PS Configuration When Both Devices Receive the Same Data
Notes to
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for the Arria II device. For Arria II GX devices, use the V
(2) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL[3..0]for an Arria II GX device, refer
Arria II Device Handbook Volume 1: Device Interfaces and Integration
For Arria II GZ devices, use the V
external host. Altera recommends powering up the configuration system I/Os with V
to
Table 9–6 on page
Figure
(MAX II Device or
Microprocessor)
External Host
ADDR
9–12:
Memory
DATA[0]
9–9. To connect MSEL[2..0] for an Arria II GZ device, refer to
Because all nSTATUS and CONF_DONE pins are tied together, if any device detects an
error, configuration stops for the entire chain and you must reconfigure the entire
chain. For example, if the first device flags an error on nSTATUS, it resets the chain by
pulling its nSTATUS pin low. This behavior is similar to a single device detecting an
error.
In your system, you can have multiple devices that contain the same configuration
data. To support this configuration scheme, all device nCE inputs are tied to GND,
while the nCEO pins are left floating. All other configuration pins (nCONFIG, nSTATUS,
DCLK, DATA0, and CONF_DONE) are connected to every device in the chain. Configuration
signals can require buffering to ensure signal integrity and prevent clock skew
problems. Ensure that the DCLK and DATA lines are buffered for every fourth device.
Devices must be the same density and package. All devices start and complete
configuration at the same time.
Figure 9–12
receiving the same configuration data.
V
CCIO
CCPGM
/ V
(1)
CCPGM
10 k
pin. V
Ω
shows a multi-device PS configuration when both Arria II devices are
V
CCIO
CCIO
/ V
(1)
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
/V
CCPGM
CCPGM
10 k Ω
GND
must be high enough to meet the V
DATA[0]
CONF_DONE
nSTATUS
nCE
nCONFIG
DCLK
Arria II Device
MSEL[n..0]
nCEO
CCIO
Table 9–7 on page
/V
N.C.
CCPGM
IH
(2)
specification of the I/O on both the device and the
.
GND
9–10.
December 2010 Altera Corporation
DATA[0]
CONF_DONE
nSTATUS
nCE
nCONFIG
DCLK
Arria II Device
MSEL[n..0]
nCEO
PS Configuration
N.C.
CCIO
(2)
pin.