EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 290

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–10
Table 9–6. Configuration Schemes for Arria II GX Devices (Part 2 of 2)
Table 9–7. Configuration Schemes for Arria II GZ Devices
Arria II Device Handbook Volume 1: Device Interfaces and Integration
AS with or without remote system upgrade
JTAG-based configuration
Notes to
(1) Configuration voltage standard applied to the V
(2) These modes are only supported when using a MAX II device or a microprocessor with flash memory for configuration. In these modes, the
(3) JTAG-based configuration takes precedence over other configuration schemes, which means the MSEL pin settings are ignored. JTAG-based
(4) Do not leave the MSEL pins floating. Connect them to V
FPP
PS
Fast AS (40 MHz)
Remote system upgrade fast AS (40 MHz)
FPP with design security feature and/or
decompression enabled
JTAG-based configuration
Notes to
(1) Arria II GZ devices only support fast AS configuration. You must use either EPCS64 or EPCS128 devices to configure an Arria II GZ device in
(2) These modes are only supported when using a MAX II device or microprocessor with flash memory for configuration. In these modes, the host
(3) The JTAG-based configuration takes precedence over other configuration schemes, which means the MSEL pin settings are ignored. The
(4) Do not leave the MSEL pins floating, connect them to V
host system must output a DCLK that is ×4 the data rate.
configuration does not support the design security or decompression features.
If you only use the JTAG configuration, Altera recommends connecting the MSEL pins to GND.
fast AS mode.
system must output a DCLK that is × 4 the data rate.
JTAG-based configuration does not support the design security or decompression features.
If you only use the JTAG configuration, Altera recommends connecting the MSEL pins to GND.
Table
Table
Configuration Scheme
9–6:
9–7:
Configuration Scheme
(1)
Table 9–7
(2)
(3)
(3)
lists the configuration schemes for Arria II GZ devices.
(1)
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
CCIO
MSEL3
power supply in which the configuration pins reside.
CCPD
(4)
0
1
1
1
CCPGM
or GND. These pins support the non-JTAG configuration scheme used in production.
MSEL2
or GND. These pins support non-JTAG configuration scheme used in production.
(4)
0
0
0
0
0
MSEL2
(4)
0
1
1
1
MSEL1
(4)
0
1
1
1
0
MSEL1
(4)
1
0
1
1
MSEL0
(4)
0
0
1
1
1
MSEL0
(4)
1
1
0
1
Fast/Standard
Fast/Standard
Fast/Standard
Fast/Standard
Fast/Standard
POR Delay
POR Delay
December 2010 Altera Corporation
Standard
Standard
—
Fast
Fast
—
Configuration Schemes
Standard (V)
Configuration
Configuration
Standard (V)
3.0, 2.5, 1.8
3.0, 2.5, 1.8
3.0, 2.5, 1.8
3.0, 2.5, 1.8
3.0, 2.5, 1.8
Voltage
3.0, 2.5
3.0, 2.5
Voltage
3.3
3.3
—
—
(1)