EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 204
EP2AGX95EF29C4N
Manufacturer Part Number
EP2AGX95EF29C4N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29C4N.pdf
(306 pages)
Specifications of EP2AGX95EF29C4N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2AGX95EF29C4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP2AGX45CU17C6N PDF datasheet
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- EP2AGX95EF29C4N PDF datasheet #6
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7–8
Figure 7–5. Number of DQ/DQS Groups per Bank in EP2AGX45 and EP2AGX65 Devices in the 572-Pin FineLine BGA
Package
Notes to
(1) All I/O pin counts include 12 dedicated clock inputs (CLK4 to CLK15) that you can use for data inputs.
(2) Arria II GX devices in the 572-pin FineLine BGA Package do not support the × 36 QDR II+/QDR II SRAM interface.
(3) Several configuration pins in Bank 6A are shared with DQ/DQS pins. You cannot use a × 4 DQ/DQS group with any of their pin members used for
Arria II Device Handbook Volume 1: Device Interfaces and Integration
configuration purposes. Ensure that the DQ/DQS groups you chose are not also used for configuration.
Figure
(Note
7–5:
1),
(2)
Figure 7–5
and EP2AGX65 devices in the 572-pin FineLine BGA package.
shows the number of DQ/DQS groups per bank in Arria II GX EP2AGX45
Devices in the 572-Pin FineLine BGA
38 User I/Os
I/O Bank 8A
38 User I/Os
I/O Bank 3A
×16/×18=1
×32/×36=0
×16/×18=1
×32/×36=0
×8/×9=2
×8/×9=2
×4=4
×4=4
EP2AGX45 and EP2AGX65
38 User I/Os
I/O Bank 4A
38 User I/Os
I/O Bank 7A
×16/×18=1
×32/×36=0
×16/×18=1
×32/×36=0
×8/×9=2
×8/×9=2
×4=4
×4=4
Chapter 7: External Memory Interfaces in Arria II Devices
50 User I/Os
I/O Bank 6A (3)
50 User I/Os
I/O Bank 5A
×16/×18=1
×32/×36=0
×16/×18=1
×32/×36=0
×8/×9=3
×8/×9=3
×4=6
×4=6
Memory Interfaces Pin Support for Arria II Devices
December 2010 Altera Corporation
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