EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 494

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–4
Arria II Device Handbook Volume 2: Transceivers
Table 2–1
on the refclk pins.
Table 2–1. Electrical Specifications for the Input Reference Clock for Arria II Devices
Figure 2–3
configured as HCSL.
Figure 2–3. Termination Scheme for a Reference Clock Signal When Configured as HCSL
Notes to
(1) No biasing is required if the reference clock signals are generated from a clock source that conforms to the PCIe
(2) Select resistor values as recommended by the PCIe clock source vendor.
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Notes to
(1) In PCI Express
(2) For an example termination scheme, refer to
(Note 1)
PCI Express (PIPE)
GIGE
XAUI
Serial RapidIO
SONET/SDH
SDI
Basic
specification.
if compliance to the PCIe protocol is required. The Quartus
external termination for the refclk pins signal if configured as HCSL.
Protocol
Figure
(1),
Table
lists the electrical specifications for the input reference clock signal driven
shows an example termination scheme for a reference clock signal when
(2)
2–1:
2–3:
REFCLK
(HCSL)
Source
PCIe
®
®
(PIPE) (PCIe) mode, you have the option of selecting the HCSL standard for the reference clock
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1.2-V PCML
1.5-V PCML
2.5-V PCML
Differential LVPECL
LVDS
1.2-V PCML
1.5-V PCML
2.5-V PCML
DIfferential LVPECL
LVDS
I/O Standard
HCSL
Rp
Rs
Rs
=
(2)
(2)
50 Ω
Figure
2–3.
®
CMU PLL and Receiver CDR Input Reference Clocking
Chapter 2: Transceiver Clocking in Arria II Devices
II software automatically selects DC coupling with
Rp
Coupling
=
DC
AC
AC
50 Ω
December 2010 Altera Corporation
REFCLK
REFCLK
Arria II
Termination
+
-
Off-chip
On-chip
On-chip