EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 301

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
AS and Fast AS Configuration (Serial Configuration Devices)
Figure 9–7. Multi-Device AS Configuration
Notes to
(1) Connect the pull-up resistors to the V
(2) Arria II devices have an option to select CLKUSR (40 MHz maximum) as the external clock source for DCLK.
(3) The MSEL pin settings vary for different configuration voltage standards and POR delay. To connect MSEL[3..0]for an Arria II GX device, refer to
(4) Connect the repeater buffers between the Arria II master and slave devices for DATA[0] and DCLK. This is to prevent any potential signal integrity
December 2010 Altera Corporation
Arria II GZ devices.
Table 9–6 on page
and clock skew problems.
Serial Configuration
Figure
Device
9–7:
1
V
DATA
DCLK
ASDI
CCIO
nCS
9–9. To connect MSEL[2..0] for an Arria II GZ device, refer to
/ V
(1)
Figure 9–7
The timing parameters for AS mode are not listed here because the t
t
for PS mode listed in
As shown in
connected together with external pull-up resistors. These pins are open-drain
bidirectional pins on the devices. When the first device asserts nCEO (after receiving all
its configuration data), it releases its CONF_DONE pin. But the subsequent devices in the
chain keep this shared CONF_DONE line low until they have received their configuration
data. When all target devices in the chain have received their configuration data and
have released CONF_DONE, the pull-up resistor drives a high level on this line and all
devices simultaneously enter initialization mode.
While you can cascade Arria II devices, you cannot cascade or chain together serial
configuration devices.
CCPGM
STATUS
10 kΩ
V
, t
CCIO
Buffers (4)
CF2ST1
CCIO
/ V
(1)
shows the pin connections for the multi-device AS configuration.
CCPGM
power supply of the I/O bank 3C for Arria II GX devices and to V
10 kΩ
Figure
, and t
V
GND
CCIO
CD2UM
9–7, the nSTATUS and CONF_DONE pins on all target devices are
10 kΩ
/ V
(1)
Table 9–12 on page
CCPGM
DATA[0]
DCLK
nCSO
ASDO
nSTATUS
CONF_DONE
nCONFIG
nCE
Arria II Device Master
timing parameters are identical to the timing parameters
CLKUSR
MSEL [n..0]
nCEO
Arria II Device Handbook Volume 1: Device Interfaces and Integration
V
9–29.
CCIO
Table 9–7 on page
(2)
(3)
/ V
CCPGM
10 kΩ
(1)
DATA[0]
DCLK
9–10.
nSTATUS
CONF_DONE
nCONFIG
nCE
Arria II Device Slave
CCPGM
at a 3.0-V power supply for
MSEL [n..0]
CF2CD
nCEO
, t
CF2ST0
(3)
N.C.
, t
CFG
9–21
,