EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 452

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–66
Table 1–17. Logic Levels for the PHY-MAC Layer for Arria II Devices
Arria II Device Handbook Volume 2: Transceivers
Power State
P0s
P0
P1
P2
0: normal mode
1: loopback mode
Don’t care
0: electrical state
1: receiver detect
Don’t care
tx_detectrxloopback Value
The PIPE interface block indicates a successful power state transition by asserting the
pipephydonestatus signal for one parallel clock cycle as specified in the PCIe
specification. The PHY-MAC layer must not request any further power state transition
until the pipephydonestatus signal has indicated the completion of the current power
state transition request.
Figure 1–63
state.
Figure 1–63. Example of Power State Transition from P0 to P2
The PCIe specification allows the PIPE interface to perform protocol functions such as
receiver detect, loopback, and beacon transmission in specified power states only.
This requires the PHY-MAC layer to drive the tx_detectrxloopback and
tx_forceelecidle signals appropriately in each power state to perform these
functions.
tx_detectrxloopback and tx_forceelecidle signals in each power state.
Transmitter Buffer Electrical Idle
The PCIe specification requires the transmitter buffer to be in electrical idle in the P1
power state, as shown in
differential and common mode output voltage levels are compliant to the PCIe Base
Specification 2.0 for both PCIe Gen1 and Gen2 data rates.
In Arria II GX and GZ transceivers, asserting the input signal tx_forceelecidle puts
the transmitter buffer in that channel in the electrical idle state.
relationship between asserting the tx_forceelecidle signal and the transmitter
buffer output on the tx_dataout port. Time T1 taken from the assertion of the
tx_forceelecidle signal to the transmitter buffer reaching electrical idle voltage
levels is pending characterization. When in the electrical idle state, the PCIe protocol
requires the transmitter buffer to stay in electrical idle for a minimum of 20 ns for both
Gen1 and Gen2 data rates.
pipephydonestatus
Table 1–17
powerdn[1:0]
shows an example waveform for a transition from the P0 to the P2 power
clock
0: must be deasserted
1: illegal mode
0: illegal mode
1: must be asserted in this state
0: illegal mode
1: must be asserted in this state
De-asserted in this state for sending beacon. Otherwise asserted.
lists the logic levels that the PHY-MAC layer must drive on the
Table
2'b00 (P0)
1–17. During electrical idle, the transmitter buffer
tx_forceelecidle Value
Chapter 1: Transceiver Architecture in Arria II Devices
2'b11 (P2)
December 2010 Altera Corporation
Figure 1–64
Functional Modes
shows the